Datasheet

DocID027096 Rev 2 111/137
STM32L073xx Electrical characteristics
117
Figure 33. SPI timing diagram - slave mode and CPHA = 0
Table 76. SPI characteristics in voltage Range 3
(1)
Symbol Parameter Conditions Min Typ Max Unit
f
SCK
1/t
c(SCK)
SPI clock frequency
Master mode
--
2
MHz
Slave mode 2
(2)
Duty
(SCK)
Duty cycle of SPI clock
frequency
Slave mode 30 50 70 %
t
su(NSS)
NSS setup time Slave mode, SPI presc = 2 4*Tpclk - -
ns
t
h(NSS)
NSS hold time Slave mode, SPI presc = 2 2*Tpclk - -
t
w(SCKH)
t
w(SCKL)
SCK high and low time Master mode Tpclk-2 Tpclk Tpclk+2
t
su(MI)
Data input setup time
Master mode 1.5 - -
t
su(SI)
Slave mode 6 - -
t
h(MI)
Data input hold time
Master mode 13.5 - -
t
h(SI)
Slave mode 16 - -
t
a(SO
Data output access time Slave mode 30 - 70
t
dis(SO)
Data output disable time Slave mode 40 - 80
t
v(SO)
Data output valid time
Slave mode - 30 70
t
v(MO)
Master mode - 7 9
t
h(SO)
Data output hold time
Slave mode 25 - -
t
h(MO)
Master mode 8 - -
1. Guaranteed by characterization results.
2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of t
v(SO)
and t
su(MI)
which has to fit
into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates
with a master having t
su(MI)
= 0 while Duty
(SCK)
= 50%.
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