Datasheet

ManualsBrandsST ManualsEmbedded Processors & ControllersMicrocontroller 32bit 192KB LQFP

This is information on a product in full production.

October 2015 DocID027096 Rev 2 1/137

STM32L073x8 STM32L073xB

STM32L073xZ

Ultra-low-power 32-bit MCU ARM

-based Cortex

-M0+, up to 192KB

Flash, 20KB SRAM, 6KB EEPROM, LCD, USB, ADC, DACs

Datasheet - production data

Features

•

Ultra-low-power platform

– 1.65 V to 3.6 V power supply

–

40 to 125 °C temperature range

– 0.29 µA Standby mode (3 wakeup pins)

– 0.43 µA Stop mode (16 wakeup lines)

– 0.86 µA Stop mode + RTC + 20 KB RAM

retention

– Down to 93 µA/MHz in Run mode

– 5 µs wakeup time (from Flash memory)

– 41 µA 12-bit ADC (conversion at 10ksps)

•

Core: ARM

32-bit Cortex

-M0+ with MPU

– From 32 kHz up to 32 MHz max.

– 0.95 DMIPS/MHz

•

Reset and supply management

– Ultra-safe, low-power BOR (brownout reset)

with 5 selectable thresholds

– Ultra-low-power POR/PDR

– Programmable voltage detector (PVD)

•

Clock sources

– 1 to 25 MHz crystal oscillator

– 32 kHz oscillator for RTC with calibration

– High speed internal 16 MHz factory-trimmed RC

(+/- 1%)

– Internal low-power 37 kHz RC

– Internal multispeed low-power 65 kHz to

4.2 MHz RC

– Internal self calibration of 48 MHz RC for USB

– PLL for CPU clock

•

Pre-programmed bootloader

– USB, USART supported

•

Development support

– Serial wire debug supported

•

Up to 84 fast I/Os (78 I/Os 5V tolerant)

•

Memories

–

Up to

192 KB Flash memory with ECC (2 banks

with read-while-write capability)

– 20KB RAM

– 6 KB of data EEPROM with ECC

– 20-byte backup register

– Sector protection against R/W operation

•

LCD driver for up to 4x52 or 8x48 segments

– Support contrast adjustment

– Support blinking mode

– Step-up converted on board

•

Rich Analog peripherals

– 12-bit ADC 1.14 Msps up to 16 channels (down

to 1.65 V)

– 2 x 12-bit channel DACs with output buffers

– 2x ultra-low-power comparators (window mode

and wake up capability, down to 1.8 V)

•

Up to 24 capacitive sensing channels supporting

touchkey, linear and rotary touch sensors

•

7-channel DMA controller, supporting ADC, SPI,

I2C, USART, DAC, Timers

•

11x peripheral communication interfaces

•

1x USB 2.0 crystal-less, battery charging detection

and LPM

•

4x USART (2 with ISO 7816, IrDA), 1x UART (low

power)

•

2x SPI 16 Mbits/s

•

3x I2C (2 with SMBus/PMBus)

•

11x timers: 2x 16-bit with up to 4 channels, 2x 16-bit

with up to 2 channels, 1x 16-bit ultra-low-power

timer, 1x SysTick, 1x RTC, 2x 16-bit basic for DAC,

and 2x watchdogs (independent/window)

•

CRC calculation unit, 96-bit unique ID

•

True RNG and firewall protection

•

All packages are ECOPACK

Table 1. Device summary

Reference Part number

STM32L073x8 STM32L073V8

STM32L073xB

STM32L073VB, STM32L073RB,

STM32L073CB

STM32L073xZ

STM32L073VZ, STM32L073RZ,

STM32L073CZ

)%*$

UFBGA100

7x7 mm

LQFP48 7 x 7 mm

LQFP64 10x10 mm

LQFP100 14x14 mm

TFBGA64

5x5 mm

)%*$

www.st.com

Downloaded from Arrow.com.

Summary of content (137 pages)

PAGE 1
STM32L073x8 STM32L073xB STM32L073xZ Ultra-low-power 32-bit MCU ARM®-based Cortex®-M0+, up to 192KB Flash, 20KB SRAM, 6KB EEPROM, LCD, USB, ADC, DACs Datasheet - production data Features • • • • • • • • • Ultra-low-power platform – 1.65 V to 3.6 V power supply – -40 to 125 °C temperature range – 0.29 µA Standby mode (3 wakeup pins) – 0.43 µA Stop mode (16 wakeup lines) – 0.
PAGE 2
Contents STM32L073xx Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 2/137 Downloaded from Arrow.com. 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.2 Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
STM32L073xx 3.18 Contents 3.17.4 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.17.5 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.17.6 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.18.1 I2C bus . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
Contents 7 STM32L073xx 6.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.3.11 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.3.13 I/O port characteristics . . . . . . . . . . .
PAGE 5
STM32L073xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . . . . . . . . .
PAGE 6
List of tables Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91.
PAGE 7
STM32L073xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42.
PAGE 8
List of figures Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. 8/137 Downloaded from Arrow.com. STM32L073xx grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 9
STM32L073xx 1 Introduction Introduction The ultra-low-power STM32L073xx are offered in 5 different package types from 48 to 100 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family.
PAGE 10
Description 2 STM32L073xx Description The ultra-low-power STM32L073xx microcontrollers incorporate the connectivity power of the universal serial bus (USB 2.0 crystal-less) with the high-performance ARM® Cortex®M0+ 32-bit RISC core operating at a 32 MHz frequency, a memory protection unit (MPU), high-speed embedded memories (up to 192 Kbytes of Flash program memory, 6 Kbytes of data EEPROM and 20 Kbytes of RAM) plus an extensive range of enhanced I/Os and peripherals.
PAGE 11
STM32L073xx 2.1 Description Device overview Table 2.
PAGE 12
Description STM32L073xx Figure 1. STM32L073xx block diagram 7HPS VHQVRU 6:' 6:' )/$6+ ((3520 %227 ),5(:$// &257(; 0 &38 )PD[ 0+] 5$0 038 '%* '0$ 19,& (;7, $ 3 % $'& $,1[ 63, 0,62 026, 6&. 166 86$57 5; 7; 576 &76 &. 7,0 FK 7,0 FK %5,'*( 3$> @ *3,2 3257 $ 3%> @ *3,2 3257 % 3&> @ 3(> @ 3+> @ > @ ,13 ,10 287 &203 ,13 ,10 287 %5,'*( /37,0 ,1 ,1 (75 287 5$0 .
PAGE 13
STM32L073xx 2.2 Description Ultra-low-power device continuum The ultra-low-power family offers a large choice of core and features, from 8-bit proprietary core up to ARM® Cortex®-M4, including ARM® Cortex®-M3 and ARM® Cortex®-M0+. The STM32Lx series are the best choice to answer your needs in terms of ultra-low-power features. The STM32 ultra-low-power series are the best solution for applications such as gaz/water meter, keyboard/mouse or fitness and healthcare application.
PAGE 14
Functional overview STM32L073xx 3 Functional overview 3.1 Low-power modes The ultra-low-power STM32L073xx support dynamic voltage scaling to optimize its power consumption in Run mode. The voltage from the internal low-drop regulator that supplies the logic can be adjusted according to the system’s maximum operating frequency and the external voltage supply. There are three power consumption ranges: • Range 1 (VDD range limited to 1.71-3.
PAGE 15
STM32L073xx • Functional overview Stop mode without RTC The Stop mode achieves the lowest power consumption while retaining the RAM and register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, HSE and LSE crystal oscillators are disabled. Some peripherals featuring wakeup capability can enable the HSI RC during Stop mode to detect their wakeup condition. The voltage regulator is in the low-power mode. The device can be woken up from Stop mode by any of the EXTI line, in 3.
PAGE 16
Functional overview STM32L073xx Table 3. Functionalities depending on the operating power supply range Functionalities depending on the operating power supply range Operating power supply range DAC and ADC operation Dynamic voltage scaling range I/O operation USB VDD = 1.65 to 1.71 V ADC only, conversion time up to 570 ksps Range 2 or range 3 Degraded speed performance Not functional VDD = 1.71 to 1.8 V(1) ADC only, Range 1, range 2 conversion time or range 3 up to 1.
PAGE 17
STM32L073xx Functional overview Table 5.
PAGE 18
Functional overview STM32L073xx Table 5. Functionalities depending on the working mode (from Run/active down to standby) (continued)(1)(2) Standby Run/Active Sleep DAC O O O O O -- Temperature sensor O O O O O -- Comparators O O O O O 16-bit timers O O O O -- LPTIMER O O O O O O IWDG O O O O O O WWDG O O O O -- -- Touch sensing controller (TSC) O O -- -- -- -- SysTick Timer O O O O GPIOs O O O O 0 µs 0.
PAGE 19
STM32L073xx 3.2 Functional overview Interconnect matrix Several peripherals are directly interconnected. This allows autonomous communication between peripherals, thus saving CPU resources and power consumption. In addition, these hardware connections allow fast and predictable latency. Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power run, Low-power sleep and Stop modes. Table 6.
PAGE 20
Functional overview 3.3 STM32L073xx ARM® Cortex®-M0+ core with MPU The Cortex-M0+ processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of embedded applications.
PAGE 21
STM32L073xx Functional overview 3.4 Reset and supply management 3.4.1 Power supply schemes 3.4.2 • VDD = 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins. • VSSA, VDDA = 1.65 to 3.6 V: external analog power supplies for ADC reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively. • VDD_USB = 1.65 to 3.6V: external power supply for USB transceiver, USB_DM (PA11) and USB_DP (PA12).
PAGE 22
Functional overview 3.4.3 STM32L073xx Voltage regulator The regulator has three operation modes: main (MR), low power (LPR) and power down. 3.5 • MR is used in Run mode (nominal regulation) • LPR is used in the Low-power run, Low-power sleep and Stop modes • Power down is used in Standby mode.
PAGE 23
STM32L073xx • Functional overview Startup clock After reset, the microcontroller restarts by default with an internal 2.1 MHz clock (MSI). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. • Clock security system (CSS) This feature can be enabled by software. If an HSE clock failure occurs, the master clock is automatically switched to HSI and a software interrupt is generated if enabled.
PAGE 24
Functional overview STM32L073xx Figure 2. Clock tree #9 (QDEOH :DWFKGRJ /6, 5& /HJHQG +6( +LJK VSHHG H[WHUQDO FORFN VLJQDO +6, +LJK VSHHG LQWHUQDO FORFN VLJQDO /6, /RZ VSHHG LQWHUQDO FORFN VLJQDO /6( /RZ VSHHG H[WHUQDO FORFN VLJQDO 06, 0XOWLVSHHG LQWHUQDO FORFN VLJQDO :DWFKGRJ /6 /6, WHPSR 57&6(/ 57& HQDEOH /6( 26& 57& /6( WHPSR /&' HQDEOH /68 /6' /6' /6' 0+] #9 /&'&/. #9 06, 5& /6, /6( 06, /HYHO VKLIWHUV #9 0&26(/ $'& HQDEOH $'&&/.
PAGE 25
STM32L073xx 3.6 Functional overview Low-power real-time clock and backup registers The real time clock (RTC) and the 5 backup registers are supplied in all modes including standby mode. The backup registers are five 32-bit registers used to store 20 bytes of user application data. They are not reset by a system reset, or when the device wakes up from Standby mode. The RTC is an independent BCD timer/counter.
PAGE 26
Functional overview 3.8 STM32L073xx Memories The STM32L073xx devices have the following features: • 20 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. With the enhanced bus matrix, operating the RAM does not lead to any performance penalty during accesses to the system bus (AHB and APB buses).
PAGE 27
STM32L073xx 3.10 Functional overview Direct memory access (DMA) The flexible 7-channel, general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with software trigger support for each channel.
PAGE 28
Functional overview STM32L073xx An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all scanned channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start triggers, to allow the application to synchronize A/D conversions and timers. 3.
PAGE 29
STM32L073xx 3.13.2 Functional overview VLCD voltage monitoring This embedded hardware feature allows the application to measure the VLCD supply voltage using the internal ADC channel ADC_IN16. As the VLCD voltage may be higher than VDDA, and thus outside the ADC input range, the ADC input is connected to LCD_VLCD2 (which provides 1/3VLCD when the LCD is configured 1/3Bias and 1/4VLCD when the LCD is configured 1/4Bias or 1/2Bias). 3.
PAGE 30
Functional overview 3.16 STM32L073xx Touch sensing controller (TSC) The STM32L073xx provide a simple solution for adding capacitive sensing functionality to any application. These devices offer up to 24 capacitive sensing channels distributed over 8 analog I/O groups. Capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric (such as glass, plastic).
PAGE 31
STM32L073xx 3.17 Functional overview Timers and watchdogs The ultra-low-power STM32L073xx devices include three general-purpose timers, one lowpower timer (LPTIM), one basic timer, two watchdog timers and the SysTick timer. Table 10 compares the features of the general-purpose and basic timers. Table 10.
PAGE 32
Functional overview 3.17.2 STM32L073xx Low-power Timer (LPTIM) The low-power timer has an independent clock and is running also in Stop mode if it is clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode. This low-power timer supports the following features: 3.17.
PAGE 33
STM32L073xx Functional overview 3.18 Communication interfaces 3.18.1 I2C bus Up to three I2C interfaces (I2C1 and I2C3) can operate in multimaster or slave modes. Each I2C interface can support Standard mode (Sm, up to 100 kbit/s), Fast mode (Fm, up to 400 kbit/s) and Fast Mode Plus (Fm+, up to 1 Mbit/s) with 20 mA output drive on some I/Os.
PAGE 34
Functional overview 3.18.2 STM32L073xx Universal synchronous/asynchronous receiver transmitter (USART) The four USART interfaces (USART1, USART2, USART4 and USART5) are able to communicate at speeds of up to 4 Mbit/s. They provide hardware management of the CTS, RTS and RS485 driver enable (DE) signals, multiprocessor communication mode, master synchronous communication and single-wire half-duplex communication mode.
PAGE 35
STM32L073xx Functional overview Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption. Higher speed clock can be used to reach higher baudrates. LPUART interface can be served by the DMA controller. 3.18.
PAGE 36
Functional overview 3.19 STM32L073xx Clock recovery system (CRS) The STM32L073xx embeds a special block which allows automatic trimming of the internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device operational range. This automatic trimming is based on the external synchronization signal, which could be either derived from USB SOF signalization, from LSE oscillator, from an external signal on CRS_SYNC pin or generated by user software.
PAGE 37
STM32L073xx 4 Pin descriptions Pin descriptions ϭϬϬ ϵϵ ϵϴ ϵϳ ϵϲ ϵϱ ϵϰ ϵϯ ϵϮ ϵϭ ϵϬ ϴϵ ϴϴ ϴϳ ϴϲ ϴϱ ϴϰ ϴϯ ϴϮ ϴϭ ϴϬ ϳϵ ϳϴ ϳϳ ϳϲ s s^^ W ϭ W W W KK7 3% 3% W W W W ϳ W ϲ W ϱ W ϰ W ϯ W Ϯ W ϭ W Ϭ W ϭϮ W ϭϭ W ϭϬ W ϭϱ W ϭϰ Figure 3.
PAGE 38
Pin descriptions STM32L073xx Figure 4.
PAGE 39
STM32L073xx Pin descriptions 9'' 966 3% 3% %227 3% 3% 3% 3% 3% 3' 3& 3& 3& 3$ 3$ Figure 5.
PAGE 40
Pin descriptions STM32L073xx Figure 6.
PAGE 41
STM32L073xx Pin descriptions 9'' 966 3% 3% %227 3% 3% 3% 3% 3% 3$ 3$ Figure 7.
PAGE 42
Pin descriptions STM32L073xx Table 15. Legend/abbreviations used in the pinout table (continued) Name Pin functions Abbreviation Definition Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers Table 16.
PAGE 43
STM32L073xx Pin descriptions Table 16.
PAGE 44
Pin descriptions STM32L073xx Table 16.
PAGE 45
STM32L073xx Pin descriptions Table 16.
PAGE 46
Pin descriptions STM32L073xx Table 16.
PAGE 47
STM32L073xx Pin descriptions Table 16.
PAGE 48
Pin descriptions STM32L073xx Table 16.
PAGE 49
STM32L073xx Pin descriptions Table 16. STM32L073xx pin definition (continued) LQFP48 LQFP64 TFBGA64 LQFP100 UFBGA100 Pin name (function after reset) Pin type I/O structure Note Pin number Alternate functions 47 63 D4 99 D3 VSS S - - - - 48 64 E4 100 C4 VDD S - - - - Additional functions 1. PA4 offers a reduced touch sensing sensitivity. It is thus recommended to use it as sampling capacitor I/O. 2. These pins are powered by VDD_USB.
PAGE 50
/137 Downloaded from Arrow.com.
PAGE 51
Downloaded from Arrow.com.
PAGE 52
/137 Downloaded from Arrow.com.
PAGE 53
Downloaded from Arrow.com.
PAGE 54
/137 Downloaded from Arrow.com.
PAGE 55
Downloaded from Arrow.com. USB_CRS_SYNC - - - PH1 PH9 PH10 - - - - SPI1/SPI2/I2S2 /I2C1/LCD/TIM2/21 SPI1/SPI2/ I2S2/USART1/2/ LPUART1/USB/ LPTIM1/TSC/ TIM2/21/22/ EVENTOUT/ SYS_AF PH0 Port AF1 AF0 - - - - SPI1/SPI2/I2S2/ LPUART1/ USART5/USB/ LPTIM1/TIM2/3/ EVENTOUT/ SYS_AF AF2 - - - - I2C1/TSC/ EVENTOUT AF3 - - - - I2C1/USART1/2/ LPUART1/ TIM3/22/ EVENTOUT AF4 Table 22.
PAGE 56
Memory mapping 5 STM32L073xx Memory mapping Figure 8. Memory map [)))) )))) [( [( [ ))) &RUWH[ 0 SHULSKHUDOV )/0/24 [ RESERVED [& [ )) !(" [ RESERVED [$ [ [ ))) )))) 2SWLRQ E\WHV !0" [ [ 6\VWHP PHPRU\ !0" [ [ RESERVED [ 3HULSKHUDOV [ RESERVED [ 65$0 [ 'DWD ((3520 EDQN 'DWD ((3520 EDQN )ODVK SURJUDP
PAGE 57
STM32L073xx Electrical characteristics 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
PAGE 58
Electrical characteristics 6.1.6 STM32L073xx Power supply scheme Figure 11. Power supply scheme 287 *3 , 2V ,1 9'' 9'' /HYHO VKLIWHU 6WDQGE\ SRZHU FLUFXLWU\ 26& 57& :DNH XS ORJLF 57& EDFNXS UHJLVWHUV ,2 /RJLF .HUQHO ORJLF &38 'LJLWDO 0HPRULHV 5HJXODWRU 1 î Q) î ) 966 9''$ 9''$ 95() Q) ) Q) ) 95() 95() $'& '$& $QDORJ 5& 3// &203 « 966$ 9/&' 966 966 9''B86% /&' 86% WUDQVFHLYHU 06Y 9 58/137 Downloaded from Arrow.com.
PAGE 59
STM32L073xx 6.1.7 Electrical characteristics Optional LCD power supply scheme Figure 12. Optional LCD power supply scheme 96(/ 9'' 1 [ Q) [ ) 2SWLRQ 9'' 6WHS XS &RQYHUWHU 9/&' Q) /&' 9/&' 2SWLRQ &(;7 966 06Y 9 1. Option 1: LCD power supply is provided by a dedicated VLCD supply source, VSEL switch is open. 2.
PAGE 60
Electrical characteristics 6.2 STM32L073xx Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 23: Voltage characteristics, Table 24: Current characteristics, and Table 25: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 23.
PAGE 61
STM32L073xx Electrical characteristics Table 24. Current characteristics Symbol Ratings Max.
PAGE 62
Electrical characteristics STM32L073xx 6.3 Operating conditions 6.3.1 General operating conditions Table 26. General operating conditions Symbol Parameter Conditions Min Max fHCLK Internal AHB clock frequency - 0 32 fPCLK1 Internal APB1 clock frequency - 0 32 fPCLK2 Internal APB2 clock frequency - 0 32 BOR detector disabled 1.65 3.6 BOR detector enabled, at power on 1.8 3.6 BOR detector disabled, after power on 1.65 3.
PAGE 63
STM32L073xx Electrical characteristics Table 26.
PAGE 64
Electrical characteristics 6.3.2 STM32L073xx Embedded reset and power control block characteristics The parameters given in the following table are derived from the tests performed under the ambient temperature condition summarized in Table 26. Table 27.
PAGE 65
STM32L073xx Electrical characteristics Table 27. Embedded reset and power control block characteristics (continued) Symbol Parameter VPVD6 Conditions PVD threshold 6 Hysteresis voltage Vhyst Min Typ Max Falling edge 2.97 3.05 3.09 Rising edge 3.08 3.15 3.20 BOR0 threshold - 40 - All BOR and PVD thresholds excepting BOR0 - 100 - Unit V mV 1. Guaranteed by characterization results. 2. Valid for device version without BOR at power up.
PAGE 66
Electrical characteristics STM32L073xx Table 29. Embedded internal reference voltage(1) (continued) Symbol Parameter Conditions Min Typ Max Unit Consumption of reference voltage buffer for VREF_OUT and COMP - - 730 1200 nA VREFINT_DIV1(4) 1/4 reference voltage - 24 25 26 VREFINT_DIV2(4) 1/2 reference voltage - 49 50 51 VREFINT_DIV3(4) 3/4 reference voltage - 74 75 76 ILPBUF(4) % VREFINT 1.
PAGE 67
STM32L073xx Electrical characteristics Table 30. Current consumption in Run mode, code with data processing running from Flash memory Symbol Parameter fHCLK (MHz) Typ Max(1) 1 190 250 2 345 380 4 650 670 4 0,8 0,86 8 1,55 1,7 16 2,95 3,1 8 1,9 2,1 16 3,55 3,8 32 6,65 7,2 0,065 39 130 0,524 115 210 4,2 700 770 Range2, Vcore=1.5 V VOS[1:0]=10 16 2,9 3,2 Range1, Vcore=1.8 V VOS[1:0]=01 32 Condition Range3, Vcore=1.
PAGE 68
Electrical characteristics STM32L073xx Figure 14. IDD vs VDD, at TA= 25/55/85/105 °C, Run mode, code running from Flash memory, Range 2, HSE, 1WS ,'' P$ 9'' 9 & & & & & & 06Y 9 Figure 15.
PAGE 69
STM32L073xx Electrical characteristics Table 32. Current consumption in Run mode, code with data processing running from RAM Symbol Parameter fHCLK (MHz) Typ Max(1) 1 175 230 2 315 360 4 570 630 4 0,71 0,78 8 1,35 1,6 16 2,7 3 8 1,7 1,9 16 3,2 3,7 32 6,65 7,1 0,065 38 98 0,524 105 160 4,2 615 710 Range2, Vcore=1.5 V VOS[1:0]=10 16 2,85 3 Range1, Vcore=1.8 V VOS[1:0]=01 32 Condition Range3, Vcore=1.
PAGE 70
Electrical characteristics STM32L073xx Table 34. Current consumption in Sleep mode Symbol Parameter fHCLK (MHz) Typ Max(1) 1 43,5 110 2 72 140 4 130 200 4 160 220 8 305 380 16 590 690 8 370 460 16 715 840 32 1650 2000 0,065 18 93 0,524 31,5 110 4,2 140 230 Range2, Vcore=1.5 V VOS[1:0]=10 16 665 850 Range1, Vcore=1.
PAGE 71
STM32L073xx Electrical characteristics Table 35.
PAGE 72
Electrical characteristics STM32L073xx Figure 16. IDD vs VDD, at TA= 25 °C, Low-power run mode, code running from RAM, Range 3, MSI (Range 0) at 64 KHz, 0 WS ,'' P$ ( ( ( ( ( ( ( ( ( 9'' 9 06Y 9 Table 36.
PAGE 73
STM32L073xx Electrical characteristics Table 37. Typical and maximum current consumptions in Stop mode Symbol Parameter Max(1) Unit Conditions Typ TA = − 40 to 25°C 0,43 1,00 TA = 55°C 0,735 2,50 TA= 85°C 2,25 4,90 TA = 105°C 5,3 13,00 TA = 125°C 12,5 28,00 IDD (Stop) Supply current in Stop mode µA 1. Guaranteed by characterization results at 125 °C, unless otherwise specified. Figure 17.
PAGE 74
Electrical characteristics STM32L073xx Figure 18. IDD vs VDD, at TA= 25/55/85/105/125 °C, Stop mode with RTC disabled, all clocks off ( ( ( ,'' P$ ( ( ( ( 9'' 9 & & & & & & 06Y 9 Table 38.
PAGE 75
STM32L073xx Electrical characteristics Table 39.
PAGE 76
Electrical characteristics STM32L073xx On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in the following tables. The MCU is placed under the following conditions: • all I/O pins are in input mode with a static value at VDD or VSS (no load) • all peripherals are disabled unless otherwise mentioned • the given value is calculated by measuring the current consumption – with all peripherals clocked off – with only one peripheral clocked on Table 40.
PAGE 77
STM32L073xx Electrical characteristics Table 40. Peripheral current consumption in Run or Sleep mode(1) (continued) Typical consumption, VDD = 3.0 V, TA = 25 °C Peripheral ADC1(2) Range 2, Range 3, Range 1, VCORE=1.8 V VCORE=1.5 V VCORE=1.2 V VOS[1:0] = 01 VOS[1:0] = 10 VOS[1:0] = 11 Low-power sleep and run 5.5 5 3.5 4 4 3 3 2.5 USART1 14.5 11.5 9.5 12 TIM21 7.5 6 5 5.5 TIM22 7 6 5 6 FIREWALL 1.5 1 1 0.5 DBGMCU 1.5 1 1 0.5 SYSCFG 2.5 2 2 1.
PAGE 78
Electrical characteristics STM32L073xx Table 41. Peripheral current consumption in Stop and Standby mode(1) Symbol IDD(PVD / BOR) - IREFINT - - Typical consumption, TA = 25 °C Peripheral LSE Low drive(2) VDD=1.8 V VDD=3.0 V 0.7 1.2 - 1.7 0.11 0,13 - LSI 0.27 0.31 - IWDG 0.2 0.3 - LPTIM1, Input 100 Hz 0.01 0,01 - LPTIM1, Input 1 MHz 11 12 - LPUART1 - 0,5 - RTC 0.16 0,3 - LCD1 (static duty) 0.15 0.15 - LCD1 (1/8 duty) 1.6 2.6 Unit µA µA 1.
PAGE 79
STM32L073xx Electrical characteristics Table 42. Low-power mode wakeup timings Symbol tWUSLEEP Parameter Conditions Wakeup from Sleep mode tWUSLEEP_ Wakeup from Low-power sleep mode, fHCLK = 262 kHz LP tWUSTOP tWUSTDBY Typ Max fHCLK = 32 MHz 7 8 fHCLK = 262 kHz Flash memory enabled 7 8 fHCLK = 262 kHz Flash memory switched OFF 9 10 fHCLK = fMSI = 4.2 MHz Wakeup from Stop mode, regulator in Run fHCLK = fHSI = 16 MHz mode fHCLK = fHSI/4 = 4 MHz 5.0 8 4.9 7 8.0 11 fHCLK = fMSI = 4.
PAGE 80
Electrical characteristics 6.3.6 STM32L073xx External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.The external clock signal has to respect the I/O characteristics in Section 6.3.12. However, the recommended clock input waveform is shown in Figure 19. Table 43.
PAGE 81
STM32L073xx Electrical characteristics Low-speed external user clock generated from an external source The characteristics given in the following table result from tests performed using a lowspeed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 26. Table 44.
PAGE 82
Electrical characteristics STM32L073xx High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 1 to 25 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 45.
PAGE 83
STM32L073xx Electrical characteristics Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 46.
PAGE 84
Electrical characteristics 6.3.7 STM32L073xx Internal clock source characteristics The parameters given in Table 47 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 26. High-speed internal 16 MHz (HSI16) RC oscillator Table 47. 16 MHz HSI16 oscillator characteristics Symbol fHSI16 TRIM (1)(2) ACCHSI16 (2) Parameter Conditions Min Typ Max Unit Frequency VDD = 3.
PAGE 85
STM32L073xx Electrical characteristics High-speed internal 48 MHz (HSI48) RC oscillator Table 48. HSI48 oscillator characteristics(1) Symbol fHSI48 TRIM Parameter Conditions Frequency Min Typ Max Unit - 48 - MHz (2) HSI48 user-trimming step 0.09 DuCy(HSI48) Duty cycle 0.14 (2) % (2) % 0.
PAGE 86
Electrical characteristics STM32L073xx Table 50. MSI oscillator characteristics (continued) Symbol ACCMSI DTEMP(MSI)(1) DVOLT(MSI)(1) IDD(MSI)(2) tSU(MSI) 86/137 Downloaded from Arrow.com. Parameter Condition Typ Frequency error after factory calibration - ±0.5 - MSI oscillator frequency drift 0 °C ≤ TA ≤ 85 °C - ±3 - MSI range 0 − 8.9 +7.0 MSI range 1 − 7.1 +5.0 MSI range 2 − 6.4 +4.0 MSI range 3 − 6.2 +3.0 MSI range 4 − 5.2 +3.0 MSI range 5 − 4.8 +2.
PAGE 87
STM32L073xx Electrical characteristics Table 50. MSI oscillator characteristics (continued) Symbol tSTAB(MSI)(2) fOVER(MSI) Parameter Condition MSI oscillator stabilization time MSI oscillator frequency overshoot Typ Max Unit MSI range 0 - 40 MSI range 1 - 20 MSI range 2 - 10 MSI range 3 - 4 MSI range 4 - 2.5 MSI range 5 - 2 MSI range 6, Voltage range 1 and 2 - 2 MSI range 3, Voltage range 3 - 3 Any range to range 5 - 4 Any range to range 6 - µs MHz 6 1.
PAGE 88
Electrical characteristics 6.3.9 STM32L073xx Memory characteristics RAM memory Table 52. RAM and hardware registers Symbol VRM Parameter Conditions Data retention mode(1) STOP mode (or RESET) Min Typ Max Unit 1.65 - - V 1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware registers (only in Stop mode). Flash memory and data EEPROM Table 53. Flash memory and data EEPROM characteristics Symbol Conditions Min Typ Max(1) Unit - 1.
PAGE 89
STM32L073xx Electrical characteristics Table 54.
PAGE 90
Electrical characteristics STM32L073xx Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.
PAGE 91
STM32L073xx 6.3.11 Electrical characteristics Electrical sensitivity characteristics Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination.
PAGE 92
Electrical characteristics 6.3.12 STM32L073xx I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.
PAGE 93
STM32L073xx 6.3.13 Electrical characteristics I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 60 are derived from tests performed under the conditions summarized in Table 26. All I/Os are CMOS and TTL compliant. Table 60.
PAGE 94
Electrical characteristics STM32L073xx Figure 24. VIH/VIL versus VDD (CMOS I/Os) 9,/ 9,+ 9 LQV DOO S 9 '' 3+ 3& 9 ,+PLQ W %227 IRU S H[FH 9 '' + 3 9 ,+PLQ 3& 7 %22 9 ' ' PLQ 9,+PLQ LUH UHTX DUG WDQG 6 V &02 WV 9 ,+ PHQ 9 ,/PD[ ' 9 ' ,QSXW UDQJH QRW JXDUDQWHHG &026 VWDQGDUG UHTXLUHPHQWV 9,/PD[ 9'' 9,/PD[ 9'' 9 06Y 9 Figure 25.
PAGE 95
STM32L073xx Electrical characteristics Output voltage levels Unless otherwise specified, the parameters given in Table 61 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 26. All I/Os are CMOS and TTL compliant. Table 61. Output voltage characteristics Symbol Parameter VOL(1) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin Conditions Min Max CMOS port(2), IIO = +8 mA 2.7 V ≤ VDD ≤ 3.6 V - 0.
PAGE 96
Electrical characteristics STM32L073xx Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 26 and Table 62, respectively. Unless otherwise specified, the parameters given in Table 62 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 26. Table 62.
PAGE 97
STM32L073xx Electrical characteristics Figure 26. I/O AC characteristics definition (;7(51$/ 287387 21 &/ WU ,2 RXW WI ,2 RXW 7 0D[LPXP IUHTXHQF\ LV DFKLHYHG LI WU WI 7 DQG LI WKH GXW\ F\FOH LV ZKHQ ORDGHG E\ &/ VSHFLILHG LQ WKH WDEOH ³ , 2 $& FKDUDFWHULVWLFV´ 6.3.14 DL G NRST pin characteristics The NRST pin input driver uses CMOS technology.
PAGE 98
Electrical characteristics STM32L073xx Figure 27. Recommended NRST pin protection 9'' ([WHUQDO UHVHW FLUFXLW 538 1567 ,QWHUQDO UHVHW )LOWHU ) 670 /[[ DL F 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 63. Otherwise the reset will not be taken into account by the device. 6.3.
PAGE 99
STM32L073xx Electrical characteristics Table 64. ADC characteristics (continued) Symbol Parameter CADC(2) Internal sample and hold capacitor tCAL(2)(3) Calibration time Conditions Min Typ Max Unit - - - 8 pF fADC = 16 MHz 5.2 µs - 83 1/fADC 1.5 ADC cycles + 2 fPCLK cycles - 1.5 ADC cycles + 3 fPCLK cycles - ADC clock = PCLK/2 - 4.5 - fPCLK cycle ADC clock = PCLK/4 - 8.
PAGE 100
Electrical characteristics STM32L073xx Table 65. RAIN max for fADC = 14 MHz Ts (cycles) tS (µs) RAIN max (kΩ)(1) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.96 37.2 55.5 3.96 50 71.5 5.11 NA 239.5 17.1 NA 1. Guaranteed by design. Table 66. ADC accuracy(1)(2)(3) Symbol Parameter Conditions Min Typ Max ET Total unadjusted error - 2 4 EO Offset error - 1 2.5 EG Gain error - 1 2 EL Integral linearity error - 1.5 2.
PAGE 101
STM32L073xx Electrical characteristics 2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current.
PAGE 102
Electrical characteristics STM32L073xx General PCB design guidelines Power supply decoupling should be performed as shown in Figure 30 or Figure 31, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed as close as possible to the chip. Figure 30. Power supply and reference decoupling (VREF+ not connected to VDDA) 670 /[[ 95() ) Q) 9''$ ) Q) 966$ 95()± 06 9 Figure 31.
PAGE 103
STM32L073xx 6.3.16 Electrical characteristics DAC electrical specifications Data guaranteed by design, not tested in production, unless otherwise specified. Table 67. DAC characteristics Symbol Parameter Conditions VDDA Analog supply voltage VREF+ Reference supply voltage VREF- Lower reference voltage IDDVREF+(1) Current consumption on No load, middle code (0x800) VREF+ supply No load, worst code (0x000) VREF+ = 3.
PAGE 104
Electrical characteristics STM32L073xx Table 67. DAC characteristics (continued) Symbol Parameter Conditions VDDA = 3.3V VREF+= 3.0 V TA = 0 to 50 °C Offset error temperature DAC output buffer off dOffset/dT(2) coefficient (code 0x800) V = 3.3V Min Typ Max -20 -10 0 Unit µV/°C DDA VREF+= 3.0 V TA = 0 to 50 °C DAC output buffer on 0 20 50 CL ≤ 50 pF, RL ≥ 5 kΩ DAC output buffer on - +0.1 / -0.2% +0.2 / -0.5% No RLOAD, CL ≤ 50 pF DAC output buffer off - +0 / -0.2% +0 / -0.
PAGE 105
STM32L073xx Electrical characteristics 2. Connected between DAC_OUT and VSSA. 3. Difference between two consecutive codes - 1 LSB. 4. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095. 5. Difference between the value measured at Code (0x800) and the ideal value = VREF+/2. 6. Difference between the value measured at Code (0x001) and the ideal value. 7.
PAGE 106
Electrical characteristics 6.3.18 STM32L073xx Comparators Table 70. Comparator 1 characteristics Symbol Parameter Conditions Min(1) Typ Max(1) Unit 3.6 V VDDA Analog supply voltage - 1.65 R400K R400K value - - 400 - R10K R10K value - - 10 - Comparator 1 input voltage range - 0.6 - VDDA Comparator startup time - - 7 10 - - 3 10 - - ±3 ±10 mV Comparator offset variation in VDDA = 3.
PAGE 107
STM32L073xx 6.3.19 Electrical characteristics Timer characteristics TIM timer characteristics The parameters given in the Table 72 are guaranteed by design. Refer to Section 6.3.13: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 72.
PAGE 108
Electrical characteristics STM32L073xx The analog spike filter is compliant with I2C timings requirements only for the following voltage ranges: • Fast mode Plus: 2.7 V ≤ VDD ≤ 3.6 V and voltage scaling Range 1 • Fast mode: – 2 V ≤ VDD ≤ 3.6 V and voltage scaling Range 1 or Range 2. – VDD < 2 V, voltage scaling Range 1 or Range 2, Cload < 200 pF. In other ranges, the analog filter should be disabled. The digital filter can be used instead. Note: In Standard mode, no spike filter is required.
PAGE 109
STM32L073xx Electrical characteristics Table 74. SPI characteristics in voltage Range 1 (1) (continued) Symbol Parameter Conditions Min Typ Max tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4*Tpclk - - th(NSS) NSS hold time Slave mode, SPI presc = 2 2*Tpclk - - tw(SCKH) tw(SCKL) SCK high and low time Master mode Tpclk-2 Tpclk Tpclk+ 2 Master mode 0 - - Slave mode 3 - - Master mode 7 - - Slave mode 3.
PAGE 110
Electrical characteristics STM32L073xx Table 75. SPI characteristics in voltage Range 2 (1) Symbol Parameter Conditions Min Typ Master mode fSCK 1/tc(SCK) SPI clock frequency Slave mode Transmitter 1.65
PAGE 111
STM32L073xx Electrical characteristics Table 76. SPI characteristics in voltage Range 3 (1) Symbol Parameter Min Typ fSCK 1/tc(SCK) SPI clock frequency - - Duty(SCK) Duty cycle of SPI clock frequency Slave mode 30 50 70 tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4*Tpclk - - th(NSS) NSS hold time Slave mode, SPI presc = 2 2*Tpclk - - tw(SCKH) tw(SCKL) SCK high and low time Master mode Tpclk-2 Tpclk Tpclk+2 Master mode 1.5 - - Slave mode 6 - - Master mode 13.
PAGE 112
Electrical characteristics STM32L073xx Figure 34. SPI timing diagram - slave mode and CPHA = 1(1) 166 LQSXW 6&. ,QSXW W68 166 &3+$ &32/ WF 6&. WK 166 WZ 6&.+ WZ 6&./ &3+$ &32/ WY 62 WD 62 0,62 287 3 87 WK 62 06 % 2 87 WVX 6, 026, , 1387 WU 6&. WI 6&. %, 7 287 WGLV 62 /6% 287 WK 6, % , 7 ,1 0 6% ,1 /6% ,1 DL 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Figure 35. SPI timing diagram - master mode(1) +LJK 166 LQSXW 6&. 2XWSXW &3+$ &32/ 6&.
PAGE 113
STM32L073xx Electrical characteristics I2S characteristics Table 77.
PAGE 114
Electrical characteristics STM32L073xx Figure 36. I2S slave timing diagram (Philips protocol)(1) &. ,QSXW WF &. &32/ &32/ WZ &.+ WK :6 WZ &./ :6 LQSXW WY 6'B67 WVX :6 6'WUDQVPLW /6% WUDQVPLW 06% WUDQVPLW %LWQ WUDQVPLW WVX 6'B65 /6% UHFHLYH 6'UHFHLYH WK 6'B67 /6% WUDQVPLW WK 6'B65 06% UHFHLYH %LWQ UHFHLYH /6% UHFHLYH DL E 1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD. 2. LSB transmit/receive of the previously transmitted byte.
PAGE 115
STM32L073xx Electrical characteristics USB characteristics The USB interface is USB-IF certified (full speed). Table 78. USB startup time Symbol tSTARTUP (1) Parameter USB transceiver startup time Max Unit 1 µs 1. Guaranteed by design. Table 79. USB DC electrical characteristics Symbol Parameter Conditions Min.(1) Max.(1) Unit - 3.0 3.6 V 0.2 - Input levels VDD USB operating voltage VDI(2) Differential input sensitivity VCM(2) Differential common mode range Includes VDI range 0.
PAGE 116
Electrical characteristics STM32L073xx Figure 38. USB timings: definition of data signal rise and fall time &URVVRYHU SRLQWV 'LIIHUHQWLDO GDWD OLQHV 9&56 966 WU WI DL Table 80. USB: full speed electrical characteristics Driver characteristics(1) Symbol Parameter Conditions Min Max Unit tr Rise time(2) CL = 50 pF 4 20 ns tf Time(2) CL = 50 pF 4 20 ns tr/tf 90 110 % 1.3 2.0 V trfm VCRS Fall Rise/ fall time matching Output signal crossover voltage 1.
PAGE 117
STM32L073xx Electrical characteristics Table 81. LCD controller characteristics (continued) Symbol ILCD(1) RHtot(2) RL (2) Parameter Min Typ Max Supply current at VDD = 2.2 V - 3.3 - Supply current at VDD = 3.0 V - 3.1 - Low drive resistive network overall value 5.28 6.6 7.
PAGE 118
Package information 7 STM32L073xx Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at www.st.com. ECOPACK® is an ST trademark. 7.1 LQFP100 package information Figure 39. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline MM C ! ! ! 3%!4).' 0,!.% # '!5'% 0,!.
PAGE 119
STM32L073xx Package information Table 82. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.000 - - 0.
PAGE 120
Package information STM32L073xx Figure 40. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint AI C 1. Dimensions are expressed in millimeters. Device marking for LQFP100 The following figure gives an example of topside marking versus pin 1 position identifier location. Figure 41.
PAGE 121
STM32L073xx 7.2 Package information UFBGA100 package information Figure 42. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline = 6HDWLQJ SODQH GGG = $ $ $ $ $ ( $ EDOO $ EDOO LGHQWLILHU LQGH[ DUHD = H ; ( $ = ' ' H < 0 %27720 9,(: E EDOOV HHH 0 = < ; III 0 = 723 9,(: $ & B0(B9 1. Drawing is not to scale. Table 83. UFBGA100 - 100-pin, 7 x 7 mm, 0.
PAGE 122
Package information STM32L073xx Table 83. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 43. UFBGA100 - 100-pin, 7 x 7 mm, 0.
PAGE 123
STM32L073xx Package information Device marking for UFBGA100 The following figure gives an example of topside marking versus ball A 1 position identifier location. Figure 44. UFBGA100 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ 670 / 9=, 'DWH FRGH < :: %DOO LQGHQWLILHU 5HYLVLRQ FRGH 5 06Y 9 1.
PAGE 124
Package information 7.3 STM32L073xx LQFP64 package information Figure 45. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline PP *$8*( 3/$1( F $ $ $ 6($7,1* 3/$1( & $ FFF & ' ' ' . / / 3,1 ,'(17,),&$7,21 ( ( ( E H :B0(B9 1. Drawing is not to scale. Table 85. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol 124/137 Downloaded from Arrow.com.
PAGE 125
STM32L073xx Package information Table 85. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - K 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 46.
PAGE 126
Package information STM32L073xx Device marking for LQFP64 The following figure gives an example of topside marking versus pin 1 position identifier location. Figure 47. LQFP64 marking example (package top view) 5HYLVLRQ FRGH 3URGXFW LGHQWLILFDWLRQ 5 670 / 5=7 'DWH FRGH < :: 3LQ LQGHQWLILHU 06Y 9 1.
PAGE 127
STM32L073xx 7.4 Package information TFBGA64 package information Figure 48. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball grid array package outline ( $ ( ) H + ) ' ' E EDOOV HHH 0 & % $ III 0 & $ % H $ EDOO LQGH[ DUHD 723 9,(: $ EDOO LGHQWLILHU %27720 9,(: & 6HDWLQJ SODQH GGG & $ $ $ $ 6,'( 9,(: 5 B0(B9 1. Drawing is not to scale. Table 86. TFBGA64 – 64-ball, 5 x 5 mm, 0.
PAGE 128
Package information STM32L073xx Table 86. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max e - 0.500 - - 0.0197 - F - 0.750 - - 0.0295 - ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 49. TFBGA64 – 64-ball, 5 x 5 mm, 0.
PAGE 129
STM32L073xx Package information Device marking for TFBGA64 The following figure gives an example of topside marking versus ball A 1 position identifier location. Figure 50. TFBGA64 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ / 5%+ 'DWH FRGH
PAGE 130
Package information 7.5 STM32L073xx LQFP48 package information Figure 51. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline C ! ! ! 3%!4).' 0,!.% # MM '!5'% 0,!.% CCC # + ! $ $ , , $ 0). )$%.4)&)#!4)/. 1. Drawing is not to scale. Downloaded from Arrow.com.
PAGE 131
STM32L073xx Package information Table 88. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.500 - - 0.
PAGE 132
Package information STM32L073xx Figure 52. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat recommended footprint AI D 1. Dimensions are expressed in millimeters. Device marking for LQFP48 The following figure gives an example of topside marking versus pin 1 position identifier location. Figure 53.
PAGE 133
STM32L073xx 7.6 Package information Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max × ΘJA) Where: • TA max is the maximum ambient temperature in °C, • ΘJA is the package junction-to-ambient thermal resistance, in °C/W, • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), • PINT max is the product of IDD and VDD, expressed in Watts.
PAGE 134
Package information STM32L073xx Figure 54. Thermal resistance ϰϬϬϬ ϯϱϬϬ ϯϬϬϬ 3' P: >Y&Wϰϴ ϮϱϬϬ >Y&Wϲϰ ϮϬϬϬ >Y&WϭϬϬ d& ' ϲϰ h& ' ϭϬϬ ϭϱϬϬ ϭϬϬϬ ϱϬϬ Ϭ ϭϮϱ ϭϬϬ ϳϱ ϱϬ 7HPSHUDWXUH & 7.6.1 Ϯϱ Ϭ 06Y 9 Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. 134/137 Downloaded from Arrow.com.
PAGE 135
STM32L073xx 8 Part numbering Part numbering Table 90.
PAGE 136
Revision history 9 STM32L073xx Revision history Table 91. Document revision history Date Revision 03-Aug-2015 1 Initial release 2 Changed confidentiality level to public. Updated datasheet status to “production data”. Modified ultra-low-power platform features on cover page. Changed number of GPIOs for LQFP48 for 37 in Table 2: Ultralow-power STM32L073xxx device features and peripheral counts. Changed LCD_VLCD1 into LCD_VLCD2 in Section 3.13.2: VLCD voltage monitoring.
PAGE 137
STM32L073xx IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.