Datasheet

DocID027100 Rev 4 33/149
STM32L072xx Functional overview
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3.16.4 SysTick timer
This timer is dedicated to the OS, but could also be used as a standard downcounter. It is
based on a 24-bit downcounter with autoreload capability and a programmable clock
source. It features a maskable system interrupt generation when the counter reaches ‘0’.
3.16.5 Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 37 kHz internal RC and, as it operates independently of the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes. The counter
can be frozen in debug mode.
3.16.6 Window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.17 Communication interfaces
3.17.1 I
2
C bus
Up to three I
2
C interfaces (I2C1 and I2C3) can operate in multimaster or slave modes.
Each I
2
C interface can support Standard mode (Sm, up to 100 kbit/s), Fast mode (Fm, up to
400 kbit/s) and Fast Mode Plus (Fm+, up to 1 Mbit/s) with 20 mA output drive on some I/Os.
7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with
configurable mask) are also supported as well as programmable analog and digital noise
filters.
In addition, I2C1 and I2C3 provide hardware support for SMBus 2.0 and PMBus 1.1: ARP
capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts
verifications and ALERT protocol management. I2C1/I2C3 also have a clock domain
Table 11. Comparison of I2C analog and digital filters
Analog filter Digital filter
Pulse width of
suppressed spikes
≥ 50 ns
Programmable length from 1 to 15
I2C peripheral clocks
Benefits Available in Stop mode
1. Extra filtering capability vs.
standard requirements.
2. Stable length
Drawbacks
Variations depending on
temperature, voltage, process
Wakeup from Stop on address
match is not available when digital
filter is enabled.
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