Datasheet

DS10690 Rev 6 13/144
STM32L071xx Description
33
Figure 1. STM32L071xx block diagram
CORTEX M0+ CPU
Fmax:32MHz
SWD
MPU
NVIC
GPIO PORT A
GPIO PORT B
Temp
sensor
RESET & CLK
FLASH
EEPROM
BOOT
RAM
DMA1
AHB: Fmax 32MHz
CRC
BRIDGE
A
P
B
2
FIREWALL
DBG
EXTI
ADC1
SPI1
USART1
TIM21
COMP1
LSE
TIM22
BRIDGE
A
P
B
1
TIM6
RAM 1K
I2C1
I2C2
USART2
LPUART1
SPI2/I2S
TIM2
IWDG
RTC
WWDG
LPTIM1
BCKP REG
HSE HSI 16M
PLL
MSI
LSI
PMU
REGULATOR
VDD
VDDA
VREF_OUT
NRST
PVD_IN
OSC32_IN,
OSC32_OUT
OSC_IN,
OSC_OUT
WKUPx
PA[0:15]
PB[0:8]
AINx
MISO, MOSI,
SCK, NSS
RX, TX, RTS,
CTS, CK
2ch
2ch
INP, INM, OUT
IN1, IN2,
ETR, OUT
SCL, SDA,
SMBA
SCL, SDA
RX, TX, RTS,
CTS, CK
RX, TX, RTS,
CTS
MISO/MCK,
MOSI/SD,
SCK/CK, NSS/
WS
4ch
SWD
MSv35454V1
COMP2
INP, INM, OUT
TIM7
I2C3
SCL, SDA,
SMBA
USART4
RX, TX, RTS,
CTS, CK
USART5
RX, TX, RTS,
CTS, CK
TIM3
4ch
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