Datasheet

ManualsBrandsST ManualsEmbedded Processors & ControllersMicrocontroller 32bit 128KB UFQFPN

This is information on a product in full production.

August 2018 DS10690 Rev 6 1/144

STM32L071x8 STM32L071xB

STM32L071xZ

Access line ultra-low-power 32-bit MCU Arm

-based Cortex

-M0+,

up to 192KB Flash, 20KB SRAM, 6KB EEPROM, ADC

Datasheet - production data

Features

•

Ultra-low-power platform

– 1.65 V to 3.6 V power supply

–

40 to 125 °C temperature range

– 0.29 µA Standby mode (3 wakeup pins)

– 0.43 µA Stop mode (16 wakeup lines)

– 0.86 µA Stop mode + RTC + 20 KB RAM

retention

– Down to 93 µA/MHz in Run mode

– 5 µs wakeup time (from Flash memory)

– 41 µA 12-bit ADC conversion at 10 ksps

•

Core: Arm

32-bit Cortex

-M0+ with MPU

– From 32 kHz up to 32 MHz max.

– 0.95 DMIPS/MHz

•

Memories

–

Up to

192 KB Flash memory with ECC(2 banks

with read-while-write capability)

–20 KB RAM

– 6 KB of data EEPROM with ECC

– 20-byte backup register

– Sector protection against R/W operation

•

Up to 84 fast I/Os (78 I/Os 5V tolerant)

•

Reset and supply management

– Ultra-safe, low-power BOR (brownout reset)

with 5 selectable thresholds

– Ultra-low-power POR/PDR

– Programmable voltage detector (PVD)

•

Clock sources

– 1 to 25 MHz crystal oscillator

– 32 kHz oscillator for RTC with calibration

– High speed internal 16 MHz factory-trimmed RC

(+/- 1%)

– Internal low-power 37 kHz RC

– Internal multispeed low-power 65 kHz to

4.2 MHz RC

– PLL for CPU clock

•

Pre-programmed bootloader

– USART, I2C, SPI supported

•

Development support

– Serial wire debug supported

•

Rich Analog peripherals

– 12-bit ADC 1.14 Msps up to 16 channels (down

to 1.65 V)

– 2x ultra-low-power comparators (window mode

and wake up capability, down to 1.65 V)

•

7-channel DMA controller, supporting ADC, SPI,

I2C, USART, Timers

•

Up to 10x peripheral communication interfaces

–

x USART (

2 with

ISO 7816, IrDA), 1x UART

(low power)

– Up to 6x SPI 16 Mbits/s

–

x I2C (

2 with

SMBus/PMBus)

•

11x timers: 2x 16-bit with up to 4 channels, 2x 16-bit

with up to 2 channels, 1x 16-bit ultra-low-power

timer, 1x SysTick, 1x RTC, 2x 16-bit basic, and 2x

watchdogs (independent/window)

•

CRC calculation unit, 96-bit unique ID

•

All packages are ECOPACK

Table 1. Device summary

Reference Part number

STM32L071x8

STM32L071V8, STM32L071K8,

STM32L071C8

STM32L071xB

STM32L071VB, STM32L071RB,

STM32L071CB, STM32L071KB

STM32L071xZ

STM32L071VZ, STM32L071RZ,

STM32L071CZ, STM32L071KZ

FBGA

LQFP32 7x7 mm

LQFP48 7x7 mm

LQFP64 10x10 mm

LQFP100 14x14 mm

WLCSP49

(3.294x3.258 mm)

UFBGA64

TFBGA64

5x5mm

UFBGA100

7x7 mm

FBGA

UFQFPN32

5x5 mm

www.st.com

Downloaded from Arrow.com.

Summary of content (144 pages)

PAGE 1
STM32L071x8 STM32L071xB STM32L071xZ Access line ultra-low-power 32-bit MCU Arm®-based Cortex®-M0+, up to 192KB Flash, 20KB SRAM, 6KB EEPROM, ADC Datasheet - production data Features • • • • • • • • Ultra-low-power platform – 1.65 V to 3.6 V power supply – -40 to 125 °C temperature range – 0.29 µA Standby mode (3 wakeup pins) – 0.43 µA Stop mode (16 wakeup lines) – 0.
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Contents STM32L071xx Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Functional overview . . . . . . .
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STM32L071xx Contents 3.15.1 I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.15.2 Universal synchronous/asynchronous receiver transmitter (USART) . . 32 3.15.3 Low-power universal asynchronous receiver transmitter (LPUART) . . . 32 3.15.4 Serial peripheral interface (SPI)/Inter-integrated sound (I2S) . . . . . . . . 33 3.16 Cyclic redundancy check (CRC) calculation unit . . . . . . . . . . . . . . . . . . . 33 3.
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Contents 7 STM32L071xx 6.3.16 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.3.17 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 6.3.18 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 6.3.19 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Package information . . . . . . . . . . . . . . . . . .
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STM32L071xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . . . . . . . . .
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List of tables Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. 6/144 Downloaded from Arrow.com.
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STM32L071xx Table 90. List of tables Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 DS10690 Rev 6 7/144 7 Downloaded from Arrow.com.
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List of figures STM32L071xx List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41.
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STM32L071xx Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. List of figures UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Introduction 1 STM32L071xx Introduction The ultra-low-power STM32L071xx are offered in 9 different package types from 32 pins to 100 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family.
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STM32L071xx 2 Description Description The access line ultra-low-power STM32L071xx microcontrollers incorporate the highperformance Arm® Cortex®-M0+ 32-bit RISC core operating at a 32 MHz frequency, a memory protection unit (MPU), high-speed embedded memories (up to 192 Kbytes of Flash program memory, 6 Kbytes of data EEPROM and 20 Kbytes of RAM) plus an extensive range of enhanced I/Os and peripherals. The STM32L071xx devices provide high power efficiency for a wide range of performance.
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Description 2.1 STM32L071xx Device overview Table 2.
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STM32L071xx Description Figure 1.
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Description 2.2 STM32L071xx Ultra-low-power device continuum The ultra-low-power family offers a large choice of core and features, from 8-bit proprietary core up to Arm® Cortex®-M4, including Arm® Cortex®-M3 and Arm® Cortex®-M0+. The STM32Lx series are the best choice to answer your needs in terms of ultra-low-power features. The STM32 ultra-low-power series are the best solution for applications such as gaz/water meter, keyboard/mouse or fitness and healthcare application.
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STM32L071xx Functional overview 3 Functional overview 3.1 Low-power modes The ultra-low-power STM32L071xx support dynamic voltage scaling to optimize its power consumption in Run mode. The voltage from the internal low-drop regulator that supplies the logic can be adjusted according to the system’s maximum operating frequency and the external voltage supply. There are three power consumption ranges: • Range 1 (VDD range limited to 1.71-3.
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Functional overview • STM32L071xx Stop mode without RTC The Stop mode achieves the lowest power consumption while retaining the RAM and register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, HSE and LSE crystal oscillators are disabled. Some peripherals featuring wakeup capability can enable the HSI RC during Stop mode to detect their wakeup condition. The voltage regulator is in the low-power mode. The device can be woken up from Stop mode by any of the EXTI line, in 3.
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STM32L071xx Functional overview Table 3. Functionalities depending on the operating power supply range (continued) Operating power supply range(1) Functionalities depending on the operating power supply range ADC operation Dynamic voltage scaling range VDD = 2.0 to 2.4 V Conversion time up to 1.14 Msps Range 1, range 2 or range 3 VDD = 2.4 to 3.6 V Conversion time up to 1.14 Msps Range 1, range 2 or range 3 1. GPIO speed depends on VDD voltage.
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Functional overview STM32L071xx Table 5.
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STM32L071xx Functional overview Table 5. Functionalities depending on the working mode (from Run/active down to standby) (continued)(1)(2) IPs Run/Active Sleep Lowpower run Stop Lowpower sleep Standby Wakeup capability Wakeup capability 0.28 µA (No 0.4 µA (No RTC) VDD=1.8 V RTC) VDD=1.8 V Consumption VDD=1.8 to 3.6 V (Typ) Down to 140 µA/MHz (from Flash memory) Down to 37 µA/MHz (from Flash memory) Down to 8 µA 0.65 µA (with 0.8 µA (with =1.8 V RTC) VDD=1.8 V RTC) V DD Down to 4.5 µA 0.
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Functional overview STM32L071xx Table 6.
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STM32L071xx Functional overview Nested vectored interrupt controller (NVIC) The ultra-low-power STM32L071xx embed a nested vectored interrupt controller able to handle up to 32 maskable interrupt channels and 4 priority levels. The Cortex-M0+ processor closely integrates a configurable Nested Vectored Interrupt Controller (NVIC), to deliver industry-leading interrupt performance.
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Functional overview STM32L071xx internal reference voltage (VREFINT) in Stop mode. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any external reset circuit. Note: The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the startup time at power-on can be decreased down to 1 ms typically for devices with BOR inactive at power-up.
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STM32L071xx • Functional overview – 32.768 kHz low-speed external crystal (LSE) – 37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog. The LSI clock can be measured using the high-speed internal RC oscillator for greater precision. RTC clock source The LSI, LSE or HSE sources can be chosen to clock the RTC, whatever the system clock. • Startup clock After reset, the microcontroller restarts by default with an internal 2.1 MHz clock (MSI).
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Functional overview STM32L071xx Figure 2.
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STM32L071xx 3.6 Functional overview Low-power real-time clock and backup registers The real time clock (RTC) and the 5 backup registers are supplied in all modes including standby mode. The backup registers are five 32-bit registers used to store 20 bytes of user application data. They are not reset by a system reset, or when the device wakes up from Standby mode. The RTC is an independent BCD timer/counter.
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Functional overview 3.8 STM32L071xx Memories The STM32L071xx devices have the following features: • 20 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. With the enhanced bus matrix, operating the RAM does not lead to any performance penalty during accesses to the system bus (AHB and APB buses).
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STM32L071xx 3.10 Functional overview Direct memory access (DMA) The flexible 7-channel, general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with software trigger support for each channel.
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Functional overview STM32L071xx To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode. Table 7. Temperature sensor calibration values Calibration value name 3.12.
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STM32L071xx 3.14 Functional overview Timers and watchdogs The ultra-low-power STM32L071xx devices include three general-purpose timers, one lowpower timer (LPTIM), one basic timer, two watchdog timers and the SysTick timer. Table 9 compares the features of the general-purpose and basic timers. Table 9.
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Functional overview 3.14.2 STM32L071xx Low-power Timer (LPTIM) The low-power timer has an independent clock and is running also in Stop mode if it is clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode. This low-power timer supports the following features: 3.14.
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STM32L071xx Functional overview 3.15 Communication interfaces 3.15.1 I2C bus Up to three I2C interfaces (I2C1 and I2C3) can operate in multimaster or slave modes. Each I2C interface can support Standard mode (Sm, up to 100 kbit/s), Fast mode (Fm, up to 400 kbit/s) and Fast Mode Plus (Fm+, up to 1 Mbit/s) with 20 mA output drive on some I/Os.
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Functional overview 3.15.2 STM32L071xx Universal synchronous/asynchronous receiver transmitter (USART) The four USART interfaces (USART1, USART2, USART4 and USART5) are able to communicate at speeds of up to 4 Mbit/s. They provide hardware management of the CTS, RTS and RS485 driver enable (DE) signals, multiprocessor communication mode, master synchronous communication and single-wire half-duplex communication mode.
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STM32L071xx Functional overview Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption. Higher speed clock can be used to reach higher baudrates. LPUART interface can be served by the DMA controller. 3.15.
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Pin descriptions 4 STM32L071xx Pin descriptions 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD VSS PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 3.
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STM32L071xx Pin descriptions Figure 4.
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Pin descriptions STM32L071xx Figure 6.
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STM32L071xx Pin descriptions Figure 7. STM32L071xx WLCSP49 ballout 1 2 3 4 5 6 7 A VDD IO2 PA15 PB3 PB5 BOOT0 PB9 VDD B PA12 PA14 PB4 PB6 PB8 VDD PC13 C PA10 PA13 PB7 PC1 PC0 D PA8 PA11 PB1 VSS E PB15 PA9 PB2 F PB14 PB13 G PB12 VDD PC14OSC32 _IN PC15OSC32 _OUT NRST PH0OSC_IN PH1OSC_ OUT PA1 PA0 VREF+ PC2 PB11 PA7 PA4 PA2 VDDA PB10 PB0 PA6 PA5 PA3 MSv36157V3 1. The above figure shows the package top view. 2.
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Pin descriptions STM32L071xx VDD VSS PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14 Figure 8. STM32L071xx LQFP48 pinout - 7 x 7 mm 48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 34 3 33 4 32 5 31 6 LQFP48 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 VDDIO2 VSS PA13 PA12 PA11 PA10 PA9 PA8 PB15 PB14 PB13 PB12 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 VSS VDD VDD PC13 PC14-OSC32_IN PC15-OSC32_OUT PH0-OSC_IN PH1-OSC_OUT NRST VSSA VDDA PA0 PA1 PA2 MS34745V2 1.
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STM32L071xx Pin descriptions 32 31 30 29 28 27 26 25 1 24 23 2 22 3 4 VSS 21 5 20 6 19 18 7 8 9 10 11 12 13 14 15 1617 VDDIO2 PA13 PA12 PA11 PA10 PA9 PA8 VDD PA3 PA4 PA5 PA6 PA7 PB0 PB1 VSS PC14-OSC32_IN PC15-OSC32_OUT NRST VSSA VDDA PA0 PA1 PA2 BOOT0 PB7 PB6 PB5 PB4 PA14 VDD VSS Figure 10. STM32L071xx UFQFPN32 pinout MSv35461V3 1. The above figure shows the package top view. 2. PA11 and PA12 input/output (greyed out pins) are supplied by VDDIO2. Table 14.
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Pin descriptions STM32L071xx Table 15.
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STM32L071xx Pin descriptions Table 15.
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Pin descriptions STM32L071xx Table 15.
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STM32L071xx Pin descriptions Table 15.
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Pin descriptions STM32L071xx Table 15.
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STM32L071xx Pin descriptions Table 15.
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Pin descriptions STM32L071xx Table 15.
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STM32L071xx Pin descriptions Table 15.
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Downloaded from Arrow.com. - PH1 - - SPI1/SPI2/I2S2 /I2C1/TIM2/21 SPI1/SPI2/ I2S2/USART1/2/ LPUART1/ LPTIM1/ TIM2/21/22/ EVENTOUT/ SYS_AF PH0 Port AF1 AF0 - - SPI1/SPI2/I2S2/ LPUART1/ USART5/ LPTIM1/TIM2/3/ EVENTOUT/ SYS_AF AF2 - - I2C1/ EVENTOUT AF3 - - I2C1/USART1/2/ LPUART1/ TIM3/22/ EVENTOUT AF4 Table 21.
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Memory mapping 5 STM32L071xx Memory mapping Refer to the product line reference manual for details on the memory mapping as well as the boundary addresses for all peripherals. 54/144 Downloaded from Arrow.com.
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STM32L071xx Electrical characteristics 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
PAGE 56
Electrical characteristics 6.1.6 STM32L071xx Power supply scheme Figure 13. Power supply scheme OUT GP I/Os IN Level shifter Standby-power circuitry (OSC32,RTC,Wake-up logic, RTC backup registers) IO Logic Kernel logic (CPU, Digital & Memories) VDD VDD Regulator N × 100 nF + 1 × 10 μF VSS VDDA VDDA VREF 100 nF + 1 μF 100 nF + 1 μF VREF+ VREF- ADC Analog: RC,PLL,COMP, …. VSSA MSv34740V1 6.1.7 Current consumption measurement Figure 14.
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STM32L071xx 6.2 Electrical characteristics Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 22: Voltage characteristics, Table 23: Current characteristics, and Table 24: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
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Electrical characteristics STM32L071xx Table 23. Current characteristics Symbol Ratings Max.
PAGE 59
STM32L071xx Electrical characteristics 6.3 Operating conditions 6.3.1 General operating conditions Table 25. General operating conditions Symbol Parameter Conditions Min Max Unit fHCLK Internal AHB clock frequency - 0 32 fPCLK1 Internal APB1 clock frequency - 0 32 fPCLK2 Internal APB2 clock frequency - 0 32 BOR detector disabled 1.65 3.6 BOR detector enabled, at power-on 1.8 3.6 BOR detector disabled, after power-on 1.65 3.6 Must be the same voltage as VDD(1) 1.65 3.
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Electrical characteristics STM32L071xx Table 25. General operating conditions (continued) Symbol TA TJ Parameter Min Max Maximum power dissipation (range 6) –40 85 Maximum power dissipation (range 7) –40 105 Maximum power dissipation (range 3) –40 125 Junction temperature range (range 6) -40 °C ≤TA ≤85 ° –40 105 Junction temperature range (range 7) -40 °C ≤TA ≤105 °C –40 125 Junction temperature range (range 3) -40 °C ≤TA ≤125 °C –40 130 Temperature range Conditions Unit °C 1.
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STM32L071xx 6.3.2 Electrical characteristics Embedded reset and power control block characteristics The parameters given in the following table are derived from the tests performed under the ambient temperature condition summarized in Table 25. Table 26.
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Electrical characteristics STM32L071xx Table 26. Embedded reset and power control block characteristics (continued) Symbol Parameter VPVD6 Conditions PVD threshold 6 Hysteresis voltage Vhyst Min Typ Max Falling edge 2.97 3.05 3.09 Rising edge 3.08 3.15 3.20 BOR0 threshold - 40 - All BOR and PVD thresholds excepting BOR0 - 100 - Unit V mV 1. Guaranteed by characterization results. 2. Valid for device version without BOR at power up.
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STM32L071xx Electrical characteristics Table 28. Embedded internal reference voltage(1) (continued) Symbol Parameter Conditions Min Typ Max Unit Consumption of reference voltage buffer for VREF_OUT and COMP - - 730 1200 nA VREFINT_DIV1(4) 1/4 reference voltage - 24 25 26 VREFINT_DIV2(4) 1/2 reference voltage - 49 50 51 VREFINT_DIV3(4) 3/4 reference voltage - 74 75 76 ILPBUF(4) % VREFINT 1.
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Electrical characteristics STM32L071xx Table 29. Current consumption in Run mode, code with data processing running from Flash memory Symbol Parameter fHCLK (MHz) Typ Max(1) 1 190 250 2 345 380 4 650 670 4 0,8 0,86 8 1,55 1,7 16 2,95 3,1 8 1,9 2,1 16 3,55 3,8 32 6,65 7,2 0,065 39 130 0,524 115 210 4,2 700 770 Range2, Vcore=1.5 V VOS[1:0]=10 16 2,9 3,2 Range1, Vcore=1.8 V VOS[1:0]=01 32 Condition Range3, Vcore=1.
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STM32L071xx Electrical characteristics Table 30. Current consumption in Run mode vs code type, code with data processing running from Flash memory Symbol IDD (Run from Flash memory) Parameter Conditions fHCLK Range 3, VCORE=1.2 V, VOS[1:0]=11 Supply current in Run mode, code executed from Flash memory Dhrystone 650 CoreMark 655 Fibonacci fHSE = fHCLK up to 16 MHz included, fHSE = fHCLK/2 above 16 MHz (PLL ON)(1) Range 1, VCORE=1.
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Electrical characteristics STM32L071xx Figure 16. IDD vs VDD, at TA= 25/55/85/105 °C, Run mode, code running from Flash memory, Range 2, HSI16, 1WS 3.50 3.00 IDD (mA) 2.50 2.00 1.50 1.00 0.50 VDD (V) 0 1.65 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 -40 °C 25 °C 55 °C 85 °C 105 °C 125 °C MSv37844V1 Table 31. Current consumption in Run mode, code with data processing running from RAM Symbol Parameter Condition Range3, Vcore=1.
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STM32L071xx Electrical characteristics 2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register). Table 32. Current consumption in Run mode vs code type, code with data processing running from RAM(1) Symbol Parameter Conditions fHCLK Dhrystone IDD (Run from RAM) Supply current in Run mode, code executed from RAM, Flash memory switched off fHSE = fHCLK up to 16 MHz included, fHSE = fHCLK/2 above 16 MHz (PLL ON)(2) Range 3, VCORE=1.2 V, VOS[1:0]=11 Range 1, VCORE=1.
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Electrical characteristics STM32L071xx Table 33. Current consumption in Sleep mode Symbol Parameter fHCLK (MHz) Typ Max(1) 1 43,5 110 2 72 140 4 130 200 4 160 220 8 305 380 16 590 690 8 370 460 16 715 840 32 1650 2000 0,065 18 93 0,524 31,5 110 4,2 140 230 Range2, Vcore=1.5 V VOS[1:0]=10 16 665 850 Range1, Vcore=1.
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STM32L071xx Electrical characteristics 2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register). Table 34.
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Electrical characteristics STM32L071xx Figure 17. IDD vs VDD, at TA= 25 °C, Low-power run mode, code running from RAM, Range 3, MSI (Range 0) at 64 KHz, 0 WS IDD (mA) 4,5E-02 4,0E-02 3,5E-02 3,0E-02 2,5E-02 2,0E-02 1,5E-02 1,0E-02 5,0E-03 0 VDD (V) 1,65 1,8 2 2,2 2,4 2,6 2,8 3 3,2 3,4 3,6 -40 25 55 85 105 125 MSv37845V2 Table 35.
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STM32L071xx Electrical characteristics Table 36. Typical and maximum current consumptions in Stop mode Symbol Parameter Max(1) Unit Conditions Typ TA = − 40 to 25°C 0,43 1,00 TA = 55°C 0,735 2,50 TA= 85°C 2,25 4,90 TA = 105°C 5,3 13,00 TA = 125°C 12,5 28,00 IDD (Stop) Supply current in Stop mode µA 1. Guaranteed by characterization results at 125 °C, unless otherwise specified. Figure 18.
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Electrical characteristics STM32L071xx Figure 19. IDD vs VDD, at TA= 25/55/85/105/125 °C, Stop mode with RTC disabled, all clocks OFF 1.4E-02 1.2E-02 1.0E-02 IDD (mA) 8.0E-03 6.0E-03 4.0E-03 2.0E-03 VDD (V) 0 1.65 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 -40 °C 25 °C 55 °C 85 °C 105 °C 125 °C MSv37847V1 Table 37.
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STM32L071xx Electrical characteristics Table 38.
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Electrical characteristics STM32L071xx On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in the following tables. The MCU is placed under the following conditions: • all I/O pins are in input mode with a static value at VDD or VSS (no load) • all peripherals are disabled unless otherwise mentioned • the given value is calculated by measuring the current consumption – with all peripherals clocked OFF – with only one peripheral clocked on Table 39.
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STM32L071xx Electrical characteristics Table 39. Peripheral current consumption in Run or Sleep mode(1) (continued) Typical consumption, VDD = 3.0 V, TA = 25 °C Peripheral Range 2, Range 3, Range 1, VCORE=1.8 V VCORE=1.5 V VCORE=1.2 V VOS[1:0] = 01 VOS[1:0] = 10 VOS[1:0] = 11 Low-power sleep and run GPIOA 3.5 3 2.5 2.5 GPIOB 3.5 2.5 2 2.5 Cortex- GPIOC M0+ core I/O port GPIOD 8.5 6.5 5.5 7 1 0.5 0.5 0.5 GPIOE 8 6 5 6 GPIOH 1.5 1 1 0.5 CRC 1.
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Electrical characteristics STM32L071xx Table 40. Peripheral current consumption in Stop and Standby mode(1) Symbol IDD(PVD / BOR) - IREFINT - - Typical consumption, TA = 25 °C Peripheral LSE Low drive(2) VDD=1.8 V VDD=3.0 V 0.7 1.2 - 1.7 0.11 0,13 - LSI 0.27 0.31 - IWDG 0.2 0.3 - LPTIM1, Input 100 Hz 0.01 0,01 - LPTIM1, Input 1 MHz 11 12 - LPUART1 - 0,5 - RTC 0.16 0,3 Unit µA 1. LPTIM, LPUART peripherals can operate in Stop mode but not in Standby mode. 2.
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STM32L071xx Electrical characteristics Table 41. Low-power mode wakeup timings (continued) Symbol tWUSTOP tWUSTDBY Parameter Conditions Typ Max fHCLK = fMSI = 4.2 MHz Wakeup from Stop mode, regulator in Run fHCLK = fHSI = 16 MHz mode fHCLK = fHSI/4 = 4 MHz 5.0 8 4.9 7 8.0 11 fHCLK = fMSI = 4.2 MHz Voltage range 1 5.0 8 fHCLK = fMSI = 4.2 MHz Voltage range 2 5.0 8 fHCLK = fMSI = 4.2 MHz Voltage range 3 5.0 8 7.
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Electrical characteristics 6.3.6 STM32L071xx External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.The external clock signal has to respect the I/O characteristics in Section 6.3.12. However, the recommended clock input waveform is shown in Figure 20. Table 42.
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STM32L071xx Electrical characteristics Low-speed external user clock generated from an external source The characteristics given in the following table result from tests performed using a lowspeed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 25. Table 43.
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Electrical characteristics STM32L071xx High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 1 to 25 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 44.
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STM32L071xx Electrical characteristics Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 45.
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Electrical characteristics 6.3.7 STM32L071xx Internal clock source characteristics The parameters given in Table 46 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 25. High-speed internal 16 MHz (HSI16) RC oscillator Table 46. 16 MHz HSI16 oscillator characteristics Symbol fHSI16 TRIM (1)(2) ACCHSI16 (2) Parameter Conditions Min Typ Max Unit Frequency VDD = 3.
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STM32L071xx Electrical characteristics Low-speed internal (LSI) RC oscillator Table 47. LSI oscillator characteristics Symbol Parameter Min Typ Max Unit fLSI(1) LSI frequency 26 38 56 kHz DLSI(2) LSI oscillator frequency drift 0°C ≤TA ≤ 85°C -10 - 4 % LSI oscillator startup time - - 200 µs LSI oscillator power consumption - 400 510 nA tsu(LSI)(3) IDD(LSI) (3) 1. Guaranteed by test in production. 2.
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Electrical characteristics STM32L071xx Table 48. MSI oscillator characteristics (continued) Symbol IDD(MSI)(2) tSU(MSI) tSTAB(MSI)(2) fOVER(MSI) Parameter MSI oscillator power consumption MSI oscillator startup time MSI oscillator stabilization time MSI oscillator frequency overshoot Condition Typ MSI range 0 0.75 - MSI range 1 1 - MSI range 2 1.5 - MSI range 3 2.5 - MSI range 4 4.
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STM32L071xx 6.3.8 Electrical characteristics PLL characteristics The parameters given in Table 49 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 25. Table 49.
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Electrical characteristics STM32L071xx Table 51. Flash memory and data EEPROM characteristics Symbol IDD Min Typ Max(1) Unit Average current during the whole programming / erase operation - 500 700 µA Maximum current (peak) TA = 25 °C, VDD = 3.6 V during the whole programming / erase operation - 1.5 2.5 mA Parameter Conditions 1. Guaranteed by design. Table 52.
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STM32L071xx 6.3.10 Electrical characteristics EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs.
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Electrical characteristics STM32L071xx To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports).
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STM32L071xx 6.3.11 Electrical characteristics Electrical sensitivity characteristics Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination.
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Electrical characteristics 6.3.12 STM32L071xx I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.
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STM32L071xx 6.3.13 Electrical characteristics I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 58 are derived from tests performed under the conditions summarized in Table 25. All I/Os are CMOS and TTL compliant. Table 58.
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Electrical characteristics STM32L071xx Figure 25. VIH/VIL versus VDD (CMOS I/Os) VIL/VIH (V) ins (all p /1 0.59 V DD+ 15, PH0 9 .3 =0 , PC V IHmin t BOOT0 0.38 for + p 5V DD H0/1 exce = 0.4 ,P V IHmin 0, PC15 T BOO V DD min ard tand Ss CMO VIHmin 2.0 ts V IH men = 0.7 ire requ V DD V ILmax 1.3 = 0.3 Input range not guaranteed CMOS standard requirements VILmax = 0.3VDD VILmax 0.7 0.6 VDD (V) 2.0 2.7 3.0 3.3 3.6 MSv34789V1 Figure 26.
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STM32L071xx Electrical characteristics Output voltage levels Unless otherwise specified, the parameters given in Table 59 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 25. All I/Os are CMOS and TTL compliant. Table 59. Output voltage characteristics Symbol Parameter VOL(1) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin Conditions Min Max CMOS port(2), IIO = +8 mA 2.7 V ≤ VDD ≤ 3.6 V - 0.
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Electrical characteristics STM32L071xx Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 27 and Table 60, respectively. Unless otherwise specified, the parameters given in Table 60 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 25. Table 60.
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STM32L071xx Electrical characteristics Figure 27. I/O AC characteristics definition 90% 10% 50% 50% 90% 10% EXTERNAL OUTPUT ON CL tr(IO)out tf(IO)out T Maximum frequency is achieved if (tr + tf) ≤ (2/3)T and if the duty cycle is (45-55%) when loaded by CL specified in the table “ I/O AC characteristics”. ai14131d 6.3.14 NRST pin characteristics The NRST pin input driver uses CMOS technology.
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Electrical characteristics STM32L071xx Figure 28. Recommended NRST pin protection ([WHUQDO UHVHW FLUFXLW 9'' 538 1567 ,QWHUQDO UHVHW )LOWHU ) 06 9 1. The reset network protects the device against parasitic resets. 2. The external capacitor must be placed as close as possible to the device. 3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 61. Otherwise the reset will not be taken into account by the device. 6.3.
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STM32L071xx Electrical characteristics Table 62. ADC characteristics (continued) Symbol Conditions Min Typ Max Unit See Equation 1 and Table 63 for details - - 50 kΩ Sampling switch resistance - - - 1 kΩ CADC(3) Internal sample and hold capacitor - - - 8 pF tCAL(3)(5) Calibration time RAIN(3) RADC(3)(4) Parameter External input impedance fADC = 16 MHz 5.2 µs - 83 1/fADC 1.5 ADC cycles + 2 fPCLK cycles - 1.5 ADC cycles + 3 fPCLK cycles - ADC clock = PCLK/2 - 4.
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Electrical characteristics STM32L071xx Equation 1: RAIN max formula TS - – R ADC R AIN < --------------------------------------------------------------N+2 f ADC × C ADC × ln ( 2 ) The simplified formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 63. RAIN max for fADC = 16 MHz(1) Ts (cycles) tS (µs) RAIN max for fast channels (kΩ) 1.5 0.09 3.5 RAIN max for standard channels (kΩ) VDD > 1.
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STM32L071xx Electrical characteristics Table 64. ADC accuracy(1)(2)(3) (continued) Symbol Parameter Conditions Min Typ Max ET Total unadjusted error - 2 5 EO Offset error - 1 2.5 EG Gain error - 1 2 EL Integral linearity error - 1.5 3 - 1 2 1.65 V < VREF+
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Electrical characteristics STM32L071xx Figure 30. Typical connection diagram using the ADC VDDA VT RAIN(1) VAIN AINx Cparasitic VT Sample and hold ADC converter RADC 12-bit converter IL±50nA CADC MSv34712V1 1. Refer to Table 62: ADC characteristics for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy.
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STM32L071xx Electrical characteristics Figure 32. Power supply and reference decoupling (VREF+ connected to VDDA) STM32Lxx VREF+/VDDA 1 μF // 100 nF VREF–/VSSA MS39602V1 6.3.16 Temperature sensor characteristics Table 65.
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Electrical characteristics 6.3.17 STM32L071xx Comparators Table 67. Comparator 1 characteristics Symbol Parameter Conditions Min(1) Typ Max(1) Unit 3.6 V VDDA Analog supply voltage - 1.65 R400K R400K value - - 400 - R10K R10K value - - 10 - Comparator 1 input voltage range - 0.6 - VDDA Comparator startup time - - 7 10 - - 3 10 - - ±3 ±10 mV Comparator offset variation in VDDA = 3.
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STM32L071xx 6.3.18 Electrical characteristics Timer characteristics TIM timer characteristics The parameters given in the Table 69 are guaranteed by design. Refer to Section 6.3.13: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 69.
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Electrical characteristics STM32L071xx The analog spike filter is compliant with I2C timings requirements only for the following voltage ranges: • Fast mode Plus: 2.7 V ≤VDD ≤3.6 V and voltage scaling Range 1 • Fast mode: – 2 V ≤VDD ≤3.6 V and voltage scaling Range 1 or Range 2. – VDD < 2 V, voltage scaling Range 1 or Range 2, Cload < 200 pF. In other ranges, the analog filter should be disabled. The digital filter can be used instead. Note: In Standard mode, no spike filter is required. Table 70.
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STM32L071xx Electrical characteristics Table 71. SPI characteristics in voltage Range 1 (1) (continued) Symbol Parameter Conditions Min Typ Max tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4*Tpclk - - th(NSS) NSS hold time Slave mode, SPI presc = 2 2*Tpclk - - tw(SCKH) tw(SCKL) SCK high and low time Master mode Tpclk-2 Tpclk Tpclk+ 2 Master mode 0 - - Slave mode 3 - - Master mode 7 - - Slave mode 3.
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Electrical characteristics STM32L071xx Table 72. SPI characteristics in voltage Range 2 (1) Symbol Parameter Conditions Min Typ Master mode fSCK 1/tc(SCK) SPI clock frequency Slave mode Transmitter 1.65
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STM32L071xx Electrical characteristics Table 73. SPI characteristics in voltage Range 3 (1) Symbol Parameter fSCK 1/tc(SCK) SPI clock frequency Duty(SCK) Duty cycle of SPI clock frequency tsu(NSS) Min Typ - - Slave mode 30 50 70 NSS setup time Slave mode, SPI presc = 2 4*Tpclk - - th(NSS) NSS hold time Slave mode, SPI presc = 2 2*Tpclk - - tw(SCKH) tw(SCKL) SCK high and low time Master mode Tpclk-2 Tpclk Tpclk+2 Master mode 1.5 - - Slave mode 6 - - Master mode 13.
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Electrical characteristics STM32L071xx Figure 33. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) tsu(NSS) th(NSS) tw(SCKH) tr(SCK) SCK input CPHA=0 CPOL=0 CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) th(SO) First bit OUT MISO output tf(SCK) Next bits OUT tdis(SO) Last bit OUT th(SI) tsu(SI) First bit IN MOSI input Next bits IN Last bit IN MSv41658V1 Figure 34.
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STM32L071xx Electrical characteristics Figure 35. SPI timing diagram - master mode(1) High NSS input SCK Output CPHA= 0 CPOL=0 SCK Output tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) MSB IN tr(SCK) tf(SCK) BIT6 IN LSB IN th(MI) MOSI OUTPUT MSB OUT B I T1 OUT tv(MO) LSB OUT th(MO) ai14136d 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. DS10690 Rev 6 109/144 111 Downloaded from Arrow.com.
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Electrical characteristics STM32L071xx I2S characteristics Table 74.
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STM32L071xx Electrical characteristics Figure 36. I2S slave timing diagram (Philips protocol)(1) 1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 37. I2S master timing diagram (Philips protocol)(1) 1. Guaranteed by characterization results. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.
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Package information 7 STM32L071xx Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at www.st.com. ECOPACK® is an ST trademark. 7.1 LQFP100 package information Figure 38. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline 0.
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STM32L071xx Package information Table 75. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.000 - - 0.4724 - E 15.800 16.000 16.200 0.6220 0.6299 0.
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Package information STM32L071xx Device marking for LQFP100 The following figure gives an example of topside marking versus pin 1 position identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 40. LQFP100 marking example (package top view) Product identification(1) STM32L071 VZT6 R Revision code Date code Y WW Pin 1 indentifier MSv39395V1 1.
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STM32L071xx 7.2 Package information UFBGA100 package information Figure 41. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline Z Seating plane ddd Z A4 A3 A2 A1 A E1 A1 ball identifier Z e A1 ball index area X E A Z D1 D e Y M 12 1 BOTTOM VIEW Øb (100 balls) Ø eee M Z Y X Ø fff M Z TOP VIEW A0C2_ME_V5 1. Drawing is not to scale. Table 76. UFBGA100 - 100-pin, 7 x 7 mm, 0.
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Package information STM32L071xx Table 76. UFBGA100 - 100-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 42. UFBGA100 - 100-pin, 7 x 7 mm, 0.
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STM32L071xx 7.3 Package information LQFP64 package information Figure 43. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline 0.25 mm GAUGE PLANE c A1 A A2 SEATING PLANE C A1 ccc C D D1 D3 K L L1 33 48 32 49 64 PIN 1 IDENTIFICATION E E1 E3 b 17 16 1 e 5W_ME_V3 1. Drawing is not to scale. Table 78. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.
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Package information STM32L071xx Table 78. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - K 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 44.
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STM32L071xx Package information Device marking for LQFP64 The following figure gives an example of topside marking versus pin 1 position identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 45. LQFP64 marking example (package top view) Revision code Product identification(1) R STM32L 071RBT6 Date code Y WW Pin 1 indentifier MSv39396V1 1.
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Package information 7.4 STM32L071xx UFBGA64 package information Figure 46. UFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package outline Z Seating plane ddd Z A4 A3 A2 A1 A E1 e A1 ball A1 ball identifier index area F X E A F D1 D e Y H 8 1 BOTTOM VIEW Øb (64 balls) Ø eee M Z Y X Ø fff M Z TOP VIEW A019_ME_V1 1. Drawing is not to scale. Table 79. UFBGA64 – 64-ball, 5 x 5 mm, 0.
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STM32L071xx Package information Table 79. UFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch ultra profile fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 47. UFBGA64 – 64-ball, 5 x 5 mm, 0.
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Package information 7.5 STM32L071xx TFBGA64 package information Figure 48. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball grid array package outline E1 A E F e H F D D1 Øb (64 balls) Ø eee M C B A Ø fff M C A B e 1 A1 ball index area TOP VIEW A1 ball identifier 8 BOTTOM VIEW C Seating plane ddd C A4 A2 A1 A SIDE VIEW R8_ME_V4 1. Drawing is not to scale. Table 81. TFBGA64 – 64-ball, 5 x 5 mm, 0.
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STM32L071xx Package information Table 81. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball grid array package outline (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 49. TFBGA64 – 64-ball, 5 x 5 mm, 0.
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Package information STM32L071xx Device marking for TFBGA64 The following figure gives an example of topside marking versus ball A 1 position identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 50. TFBGA64 marking example (package top view) Product identification(1) L071RZH6 Date code = Year + week Y WW Revision code R Ball A1 MSv39397V1 1.
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STM32L071xx 7.6 Package information WLCSP49 package information Figure 51. WLCSP49 - 49-pin, 3.294 x 3.258 mm, 0.4 mm pitch wafer level chip scale package outline e1 bbb Z F A1 ball location A1 G Detail A e2 E e e A D A2 Bottom view Bump side Side view A2 A3 b Bump Front view A1 eee Z Z b49x ccc ddd E ZXY Z Note 2 A1 Orientation reference Detail A (rotated 90 ) Seating plane Note 1 aaa D (4x) Top view Wafer back side A038_ME_V1 1. Drawing is not to scale.
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Package information STM32L071xx Table 83. WLCSP49 - 49-pin, 3.294 x 3.258 mm, 0.4 mm pitch wafer level chip scale package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.525 0.555 0.585 0.0207 0.0219 0.0230 A1 - 0.175 - - 0.0069 - A2 - 0.380 - - 0.0150 - - 0.025 - - 0.0010 - b(3) 0.220 0.250 0.280 0.0087 0.0098 0.0110 D 3.259 3.294 3.329 0.1283 0.1297 0.1311 E 3.223 3.258 3.293 0.1269 0.1283 0.1296 e - 0.400 - - 0.
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STM32L071xx Package information Device marking for WLCSP49 Table 84. WLCSP49 recommended PCB design rules (0.4 mm pitch) Dimension Recommended values Pitch 0.4 260 µm max. (circular) Dpad 220 µm recommended Dsm 300 µm min. (for 260 µm diameter pad) PCB pad design Non-solder mask defined via underbump allowed. The following figure gives an example of topside marking versus ball A 1 position identifier location.
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Package information 7.7 STM32L071xx LQFP48 package information Figure 54. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline c A1 A A2 SEATING PLANE C 0.25 mm GAUGE PLANE ccc C K A1 D L D1 L1 D3 36 25 37 24 48 PIN 1 IDENTIFICATION 1 12 1. Drawing is not to scale. Downloaded from Arrow.com.
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STM32L071xx Package information Table 85. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.500 - - 0.
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Package information STM32L071xx Device marking for LQFP48 The following figure gives an example of topside marking versus pin 1 position identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 56. LQFP48 marking example (package top view) Product identification(1) STM32L 071CZT7 Date code Y WW Revision code Pin 1 indentifier R MSv36160V2 1.
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STM32L071xx 7.8 Package information LQFP32 package information Figure 57. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline c A2 A1 A SEATING PLANE C 0.25 mm ccc GAUGE PLANE C K D A1 L D1 L1 D3 24 17 16 32 9 PIN 1 IDENTIFICATION 1 E E1 E3 b 25 8 e 5V_ME_V2 1. Drawing is not to scale. DS10690 Rev 6 131/144 139 Downloaded from Arrow.com.
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Package information STM32L071xx Table 86. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.600 - - 0.
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STM32L071xx Package information Device marking for LQFP32 The following figure gives an example of topside marking versus pin 1 position identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 59. LQFP32 marking example (package top view) STM32L Product identification (1) 071KZT6 Date code Y WW Revision code Pin 1 indentifier R MSv37839V1 1.
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Package information 7.9 STM32L071xx UFQFPN32 package information Figure 60. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package outline D A e A1 A3 ddd C C SEATINGPLANE D1 b e E2 b E1 E 1 L 32 D2 PIN 1 Identifier L A0B8_ME_V3 1. Drawing is not to scale. 2. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this backside pad to PCB ground. 134/144 Downloaded from Arrow.com.
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STM32L071xx Package information Table 87. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 - - 0.050 - - 0.0020 A3 - 0.152 - - 0.0060 - b 0.180 0.230 0.280 0.0071 0.0091 0.0110 D 4.900 5.000 5.100 0.1929 0.1969 0.2008 D1 3.400 3.500 3.600 0.1339 0.1378 0.1417 D2 3.400 3.500 3.600 0.1339 0.1378 0.1417 E 4.
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Package information STM32L071xx Device marking for UFQFPN32 The following figure gives an example of topside marking versus pin 1 position identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 62. UFQFPN32 marking example (package top view) Product identification(1) L071KZ6 Date code Y WW Revision code R Pin 1 indentifier MSv36159V1 1.
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STM32L071xx 7.10 Package information Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max × ΘJA) Where: • TA max is the maximum ambient temperature in ° C, • ΘJA is the package junction-to-ambient thermal resistance, in ° C/W, • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), • PINT max is the product of IDD and VDD, expressed in Watts.
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Package information STM32L071xx Figure 63. Thermal resistance 4000 3500 LQFPN32 3000 UQFN32 LQFP48 2500 WLCSP49 2000 UFBGA64 1500 LQFP100 TFBGA64 PD (mW) LQFP64 UFBGA100 1000 500 0 125 100 75 50 25 0 Temperature (°C) MSv37833V3 7.10.1 Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. 138/144 Downloaded from Arrow.com.
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STM32L071xx 8 Ordering information Ordering information Table 89.
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Revision history 9 STM32L071xx Revision history Table 90. Document revision history Date Revision 02-Sep-2015 1 Initial release 2 Changed confidentiality level to public. Updated datasheet status to “production data”. Modified ultra-low-power platform features on cover page. In Table 15: STM32L071xxx pin definition: – changed pin name to VDDIO2 for the following pins: UFQFPN32 pin 24, LQFP48 pin 36, LQFP64 pin 48, UFBGA64 pin E5, WLCSP49 pin A1, LQFP100 pin 75 and UFBGA100 pin G11.
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STM32L071xx Revision history Table 90. Document revision history Date 22-Mar-2016 Revision Changes 3 Updated number of SPIs on cover page and in Table 2: Ultra-lowpower STM32L071xx device features and peripheral counts. Changed minimum comparator supply voltage to 1.65 V on cover page. Added number of fast and standard channels in Section 3.11: Analog-to-digital converter (ADC). Updated Section 3.15.2: Universal synchronous/asynchronous receiver transmitter (USART) and Section 3.15.
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Revision history STM32L071xx Table 90. Document revision history Date 14-Sep-2017 Revision Changes 4 Memories and I/Os moved after Core in Features. Table 2: Ultra-low-power STM32L071xx device features and peripheral counts: changed number of USART for LQFP32/UFQFPN32 and added note 3. Removed column "I/O operation" from Table 3: Functionalities depending on the operating power supply range and added note related to GPIO speed.
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STM32L071xx Revision history Table 90. Document revision history Date Revision Changes 07-May-2018 5 Updated Arm logo and added Arm word mark notice in Section 1: Introduction. Removed Cortex logo. Updated Table 5: Functionalities depending on the working mode (from Run/active down to standby) to change I2C functionality to disabled in Low-power Run and Low-power Sleep modes. Section 4: Pin descriptions: – Changed PC14-OSC_IN into PC14-OSC32_IN in Figure 10: STM32L071xx UFQFPN32 pinout.
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