Datasheet

Functional overview STM32L052x6 STM32L052x8
22/143 DocID025936 Rev 8
3.4 Reset and supply management
3.4.1 Power supply schemes
• V
DD
= 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided
externally through V
DD
pins.
• V
SSA
, V
DDA
= 1.65 to 3.6 V: external analog power supplies for ADC, DAC, reset
blocks, RCs and PLL (minimum voltage to be applied to V
DDA
is 1.8 V when the DAC is
used). V
DDA
and V
SSA
must be connected to V
DD
and V
SS
, respectively.
• V
DD_USB
= 1.65 to 3.6V: external power supply for USB transceiver, USB_DM (PA11)
and USB_DP (PA12). To guarantee a correct voltage level for USB communication
V
DD_USB
must be above 3.0V. If USB is not used this pin must be tied to V
DD
. On
packages without VDD_USB pin, V
DD_USB
voltage is internally connected to V
DD
voltage.
3.4.2 Power supply supervisor
The devices have an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR) that can be coupled with a brownout reset (BOR) circuitry.
Two versions are available:
• The version with BOR activated at power-on operates between 1.8 V and 3.6 V.
• The other version without BOR operates between 1.65 V and 3.6 V.
After the V
DD
threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or
not at power-on), the option byte loading process starts, either to confirm or modify default
thresholds, or to disable the BOR permanently: in this case, the VDD min value becomes
1.65 V (whatever the version, BOR active or not, at power-on).
When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever
the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the
power ramp-up should guarantee that 1.65 V is reached on V
DD
at least 1 ms after it exits
the POR area.
Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Stop mode, it is possible to automatically switch off the
internal reference voltage (V
REFINT
) in Stop mode. The device remains in reset mode when
V
DD
is below a specified threshold, V
POR/PDR
or V
BOR
, without the need for any external
reset circuit.
Note: The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the start-
up time at power-on can be decreased down to 1 ms typically for devices with BOR inactive
at power-up.
The devices feature an embedded programmable volt
age detector (PVD) that monitors the
V
DD/VDDA
power supply and compares it to the V
PVD
threshold. This PVD offers 7 different
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when V
DD/VDDA
drops below the V
PVD
threshold and/or when
V
DD/VDDA
is higher than the V
PVD
threshold. The interrupt service routine can then generate
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
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