Datasheet

Electrical characteristics STM32L052x6 STM32L052x8
104/143 DocID025936 Rev 8
t
su(NSS)
NSS setup time
Slave mode, SPI
presc = 2
4*Tpclk - -
ns
t
h(NSS)
NSS hold time
Slave mode, SPI
presc = 2
2*Tpclk - -
t
w(SCKH)
t
w(SCKL)
SCK high and low time Master mode Tpclk-2 Tpclk
Tpclk+
2
t
su(MI)
Data input setup time
Master mode 0 - -
t
su(SI)
Slave mode 3 - -
t
h(MI)
Data input hold time
Master mode 7 - -
t
h(SI)
Slave mode 3.5 - -
t
a(SO
Data output access time Slave mode 15 - 36
t
dis(SO)
Data output disable time Slave mode 10 - 30
t
v(SO)
Data output valid time
Slave mode
1.65 V<V
DD
<3.6 V
-1841
Slave mode
2.7 V<V
DD
<3.6 V
-1825
t
v(MO)
Master mode - 4 7
t
h(SO)
Data output hold time
Slave mode 10 - -
t
h(MO)
Master mode 0 - -
1. Guaranteed by characterization results.
2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of t
v(SO)
and t
su(MI)
which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be
achieved when the SPI communicates with a master having t
su(MI)
= 0 while Duty
(SCK)
= 50%.
Table 73. SPI characteristics in voltage Range 1
(1)
(continued)
Symbol Parameter Conditions Min Typ Max Unit
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