Datasheet

Revision history STM32L031x4/6
124/126 DS10668 Rev 6
26-Sep-2017 5
Added UFQFPN48 package.
Removed column "I/O operation" from Table 3: Functionalities
depending on the operating power supply range and added note
related to GPIO speed.
In Section 4: Pin descriptions, changed USARTx_RTS and
LPUARTx_RTS into USARTx_RTS_DE and LPUARTx_RTS_DE,
respectively.
In Section 5: Memory mapping, replaced memory mapping
schematic by reference to the reference manual.
Removed note related to WLCSP25 preliminary ballout in
Table 15: Pin definitions.
Updated introduction text in Section 6.2: Absolute maximum
ratings to mention device mission profile and extended mission
profiles.
Added note in Table 52: I/O current injection susceptibility.
Updated minimum and maximum values of I/O weak pull-up
equivalent resistor (R
PU
) and weak pull-down equivalent resistor
(R
PD
) in Table 53: I/O static characteristics.
Updated minimum and maximum values of NRST weak pull-up
equivalent resistor (R
PU
) in Table 56: NRST pin characteristics.
Added note 2. related to the position of the external capacitor
below Figure 28: Recommended NRST pin protection.
Updated Section : I2C interface characteristics.
Updated Figure 31: SPI timing diagram - slave mode and CPHA =
0, Figure 32: SPI timing diagram - slave mode and CPHA = 1(1)
and Figure 33: SPI timing diagram - master mode(1).
Suppressed section USART/LPUART characteristics.
Added reference to optional marking or inset/upset marks in all
package device marking sections.
Updated Figure 36: Example of LQFP48 marking (package top
view) and Table 69: LQFP48 - 48-pin low-profile quad flat
package, 7 x 7 mm, package mechanical data.
Updated Table 71: LQFP32, 7 x 7 mm, 32-pin low-profile quad flat
package mechanical data.
Updated Figure 43: UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch
ultra thin fine pitch quad flat package outline and Table 72:
UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch
quad flat package mechanical data.
Updated Table 74: WLCSP25 - 2.097 x 2.493 mm, 0.400 mm
pitch wafer level chip scale mechanical data.
Added notes related to D and E1 in Table 76: TSSOP20 – 20-lead
thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch, package
mechanical data.
Updated Figure 55: Thermal resistance as well as the
corresponding temperature range in the note below the figure.
Renamed Section 8 into Ordering information.
Table 79. Document revision history
Date Revision Changes
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