Datasheet

DocID027973 Rev 5 87/119
STM32L011x3/4 Electrical characteristics
93
6.3.19 Communications interfaces
I
2
C interface characteristics
The
I
2
C interface meets the timings requirements of the
I
2
C-bus specification and user
manual rev. 03 for:
• Standard-mode (Sm) : with a bit rate up to 100 kbit/s
• Fast-mode (Fm) : with a bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+) : with a bit rate up to 1 Mbit/s.
The
I
2
C timing requirements are guaranteed by design when the
I
2
C peripheral is properly
configured (refer to the reference manual for details) and when the I2CCLK frequency is
greater than the minimum given in Table 63. The SDA and SCL I/O requirements are met
with the following restrictions: the SDA and SCL I/O pins are not "true" open-drain. When
configured as open-drain, the PMOS connected between the I/O pin and VDDIOx is
disabled, but is still present. Only FTf I/O pins support Fm+ low level output current
maximum requirement (refer to Section 6.3.13: I/O port characteristics for the I2C I/Os
characteristics).
All
I
2
C SDA and SCL I/Os embed an analog filter (see Table 62 for the analog filter
characteristics).
The analog spike filter is compliant with
I
2
C timings requirements only for the following
voltage ranges:
• Fast mode Plus: 2.7 V ≤
V
DD
≤ 3.6 V and voltage scaling Range 1
• Fast mode:
–2V ≤ V
DD
≤ 3.6 V and voltage scaling Range 1 or Range 2.
–V
DD
< 2 V, voltage scaling Range 1 or Range 2, C
load
< 200 pF.
In other ranges, the analog filter should be disabled. The digital filter can be used instead.
Note: In Standard mode, no spike filter is required.
Table 62. I2C analog filter characteristics
(1)
1. Guaranteed by characterization results.
Symbol Parameter Conditions Min Max Unit
t
AF
Maximum pulse width of spikes that
are suppressed by the analog filter
Range 1
50
(2)
2. Spikes with widths below t
AF(min)
are filtered.
260
(3)
3. Spikes with widths above t
AF(max)
are not filtered
nsRange 2 -
Range 3 -
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