Datasheet

DocID027973 Rev 5 81/119
STM32L011x3/4 Electrical characteristics
93
Equation 1: R
AIN
max formula
The simplified formula above (Equation 1) is used to determine the maximum external
impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
C
ADC
(3)
Internal sample and hold
capacitor
---8pF
t
CAL
(3)
Calibration time
f
ADC
= 16 MHz 5.2 µs
-831/f
ADC
W
LATENCY
ADC_DR register write
latency
ADC clock = HSI16
1.5 ADC
cycles + 2
f
PCLK
cycles
-
1.5 ADC
cycles + 3
f
PCLK
cycles
-
ADC clock = PCLK/2 - 4.5 -
f
PCLK
cycle
ADC clock = PCLK/4 - 8.5 -
f
PCLK
cycle
t
latr
(3)
Trigger conversion latency
f
ADC
= f
PCLK
/2 = 16 MHz 0.266 µs
f
ADC
= f
PCLK
/2 8.5 1/f
PCLK
f
ADC
= f
PCLK
/4 = 8 MHz 0.516 µs
f
ADC
= f
PCLK
/4 16.5 1/f
PCLK
f
ADC
= f
HSI16
= 16 MHz 0.252 - 0.260 µs
Jitter
ADC
ADC jitter on trigger
conversion
f
ADC
= f
HSI16
-1-1/f
HSI16
t
S
(3)
Sampling time
f
ADC
= 16 MHz 0.093 - 10.03 µs
- 1.5 - 239.5 1/f
ADC
t
STAB
(3)
Power-up time - 0 0 1 µs
t
ConV
(3)
Total conversion time
(including sampling time)
f
ADC
= 16 MHz 0.875 10.81 µs
-
14 to 173 (t
S
for sampling +12.5 for
successive approximation)
1/f
ADC
1. V
DDA
minimum value can be decreased in specific temperature conditions. Refer to Table 55: RAIN max for fADC = 16
MHz.
2. A current consumption proportional to the APB clock frequency has to be added (see Table 32: Peripheral current
consumption in run or Sleep mode).
3. Guaranteed by design, not tested in production.
4. Standard channels have an extra protection resistance which depends on supply voltage. Refer to Table 55: RAIN max for
fADC = 16 MHz.
Table 54. ADC characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
R
AIN
T
S
f
ADC
C
ADC
2
N2+
()ln××
----------------------------------------------------------------
R
ADC
–<
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