Datasheet

Functional overview STM32L011x3/4
18/119 DocID027973 Rev 5
3.2 Interconnect matrix
Several peripherals are directly interconnected. This allows autonomous communication
between peripherals, thus saving CPU resources and power consumption. In addition,
these hardware connections allow fast and predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power
run, Low-power sleep and Stop modes.
Comparators O O O O O O - -
16-bit timers O O O O - - - -
LPTIM O O O O O O - -
IWDG O O O O O O O O
WWDG O O O O - - - -
SysTick Timer O O O O - - - -
GPIOs O O O O O O - 2 pins
Wakeup time to
Run mode
0 µs 6 CPU cycles 3 µs
7 CPU
cycles
5µs 65µs
Consumption
V
DD
=1.8 to 3.6 V
(Typ)
Down to
128 µA/MHz
(from Flash)
Down to
31 µA/MHz
(from Flash)
Down to
7µA
Down to
3.8 µA
0.29 µA (No
RTC) V
DD
=1.8 V
0.18 µA (No
RTC) V
DD
=1.8 V
0.54 µA (with
RTC) V
DD
=1.8 V
0.41 µA (with
RTC) V
DD
=1.8 V
0.34 µA (No
RTC) V
DD
=3.0 V
0.23 µA (No
RTC) V
DD
=3.0 V
0.67 µA (with
RTC) V
DD
=3.0 V
0.53 µA (with
RTC) V
DD
=3.0 V
1. Legend:
“Y” = Yes (enable).
“O” = Optional, can be enabled/disabled by software)
“-” = Not available
2. The consumption values given in this table are preliminary data given for indication. They are subject to slight changes.
3. Some peripherals with wakeup from Stop capability can request HSI to be enabled. In this case, HSI is woken up by the
peripheral, and only feeds the peripheral which requested it. HSI is automatically put off when the peripheral does not need
it anymore.
4. UART and LPUART reception is functional in Stop mode. It generates a wakeup interrupt on Start.To generate a wakeup on
address match or received frame event, the LPUART can run on LSE clock while the UART has to wake up or keep running
the HSI clock.
5. I2C address detection is functional in Stop mode. It generates a wakeup interrupt in case of address match. It will wake up
the HSI during reception.
Table 5. Functionalities depending on the working mode
(from Run/active down to standby) (continued)
(1)(2)
IPs Run/Active Sleep
Low-
power
run
Low-
power
sleep
Stop Standby
Wakeup
capability
Wakeup
capability
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