Datasheet

DocID027973 Rev 5 117/119
STM32L011x3/4 Revision history
118
20-Jun-2016 4
Updated:
– Features in cover page: Stop mode values, channels’
number of DMA controller, I/Os’ number, number of
peripherals communication interface.
– Table 27: Current consumption in Low-power Run
mode, Table 28: Current consumption in Low-power
Sleep mode, Table 34: Low-power mode wakeup
timings, Table 36: Low-speed external user clock
characteristics
12-Sep-2017 5
Removed I/O operation from Table 3: Functionalities
depending on the operating power supply range.
Updated Section 3.4.4: Boot modes and added Note 7.
in Table 13: Pin definitions.
Changed USARTx_RTS and LPUARTx_RTS into
USARTx_RTS_DE and LPUARTx_RTS_DE,
respectively in Section 4: Pin descriptions.
In Section 5: Memory mapping, replaced memory
mapping schematic by reference to the reference
manual.
Updated introduction text in Section 6.2: Absolute
maximum ratings to mention device mission profile and
extended mission profiles.
Added note in Table 49: I/O current injection
susceptibility.
Updated minimum and maximum values of I/O weak
pull-up equivalent resistor (R
PU
) and weak pull-down
equivalent resistor (R
PD
) in Table 50: I/O static
characteristics.
Updated minimum and maximum values of NRST weak
pull-up equivalent resistor (R
PU
) in Table 53: NRST pin
characteristics. Added note 2 related to the position of
the external capacitor below Figure 26: Recommended
NRST pin protection.
Updated Section : I2C interface characteristics.
Removed section USART/LPUART characteristics.
Updated Figure 29: SPI timing diagram - slave mode
and CPHA = 0, Figure 30: SPI timing diagram - slave
mode and CPHA = 1(1) and Figure 31: SPI timing
diagram - master mode(1).
Table 77. Document revision history
Date Revision Changes
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