Datasheet

Electrical characteristics STM32L010F4/K4
76/91 DS12323 Rev 2
6.3.17 Communications interfaces
I
2
C interface characteristics
The
I
2
C interface meets the timings requirements of the
I
2
C-bus specification and user
manual rev. 03 for standard-mode (Sm) with a bit rate up to 100 kbit/s.
The
I
2
C timing requirements are guaranteed by design when the
I
2
C peripheral is properly
configured (refer to the reference manual for details) and when the I2CCLK frequency is
greater than 2 MHz. The SDA and SCL I/O requirements are met with the following
restrictions: the SDA and SCL I/O pins are not "true" open-drain. When configured as open-
drain, the PMOS connected between the I/O pin and VDDIOx is disabled, but is still present.
All
I
2
C SDA and SCL I/Os embed an analog filter (see Table 56 for the analog filter
characteristics).
Table 56. I2C analog filter characteristics
(1)
Symbol Parameter Conditions Min Max Unit
t
AF
Maximum pulse width of spikes that are
suppressed by the analog filter
Range 1
50
(2)
100
(3)
nsRange 2 -
Range 3 -
1. Guaranteed by characterization results.
2. Spikes with widths below t
AF(min)
are filtered.
3. Spikes with widths above t
AF(max)
are not filtered
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