Datasheet

DS12323 Rev 2 71/91
STM32L010F4/K4 Electrical characteristics
81
Figure 22. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The external capacitor must be placed as close as possible to the device.
3. The user must ensure that the level on the NRST pin can go below the V
IL(NRST)
max level specified in
Table 51. Otherwise the reset will not be taken into account by the device.
6.3.15 12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 52 are values derived from tests
performed under ambient temperature, f
PCLK
frequency and V
DDA
supply voltage conditions
summarized in Table 15: General operating conditions.
Note: It is recommended to perform a calibration after each power-up.
Table 51. NRST pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
IL(NRST)
(1)
1. Guaranteed by design, not tested in production.
NRST input low
level voltage
---0.3V
DD
V
V
IH(NRST)
(1)
NRST input high
level voltage
- 0.39V
DD
+ 0.59 - -
V
OL(NRST)
(1)
NRST output low
level voltage
I
OL
= 2 mA
2.7 V < V
DD
< 3.6 V
--
0.4
I
OL
= 1.5 mA
1.8 V < V
DD
< 2.7 V
--
V
hys(NRST)
(1)
NRST Schmitt
trigger voltage
hysteresis
--10%V
DD
(2)
2. 200 mV minimum value
-mV
R
PU
Weak pull-up
equivalent
resistor
(3)
3. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance is around 10%.
V
IN
= V
SS
25 45 65 kΩ
V
F(NRST)
(1)
NRST input
filtered pulse
---50ns
V
NF(NRST)
(1)
NRST input not
filtered pulse
- 350 - - ns
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