Datasheet

DS12323 Rev 2 55/91
STM32L010F4/K4 Electrical characteristics
81
6.3.6 External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the input pin is a standard GPIO.The external clock signal has to respect
the I/O characteristics in Section 6.3.12. However, the recommended clock input waveform
is shown in Figure 14.
Figure 14. High-speed external clock source AC timing diagram
Table 32. High-speed external user clock characteristics
(1)
1. Guaranteed by design, not tested in production.
Symbol Parameter Conditions Min Typ Max Unit
f
HSE_ext
User external clock source
frequency
CSS is ON or
PLL used
1832MHz
CSS is OFF,
PLL not used
0832MHz
V
HSEH
CK_IN input pin high level voltage
-
0.7V
DD
-V
DD
V
V
HSEL
CK_IN input pin low level voltage V
SS
-0.3V
DD
t
w(HSE)
t
w(HSE)
CK_IN high or low time 12 - -
ns
t
r(HSE)
t
f(HSE)
CK_IN rise or fall time - - 20
C
in(HSE)
CK_IN input capacitance - 2.6 - pF
DuCy
(HSE)
Duty cycle 45 - 55 %
I
L
CK_IN input leakage current V
SS
≤ V
IN
≤ V
DD
--±1µA
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