Datasheet

Electrical characteristics STM32L010F4/K4
40/91 DS12323 Rev 2
6.3 Operating conditions
6.3.1 General operating conditions
6.3.2 Embedded reset and power control block characteristics
The parameters given in the following table are derived from the tests performed under the
ambient temperature condition summarized in Table 15.
Table 15. General operating conditions
Symbol Parameter Conditions Min Max Unit
f
HCLK
Internal AHB clock frequency - 0 32
MHzf
PCLK1
Internal APB1 clock frequency - 0 32
f
PCLK2
Internal APB2 clock frequency - 0 32
V
DD
Standard operating voltage - 1.8 3.6 V
V
DDA
Analog operating voltage
(all features)
Must be the same voltage as V
DD
(1)
1.8 3.6 V
V
IN
Input voltage on FT and RST pins
(2)
2.0 V ≤ V
DD
≤ 3.6 V –0.3 5.5
V
1.8 V ≤ V
DD
≤ 2.0 V –0.3 5.2
Input voltage on BOOT0 pin - 0 5.5
Input voltage on TC pin - –0.3 V
DD
+ 0.3
P
D
Power dissipation at T
A
= 85 °C
(3)
TSSOP20/
LQFP32
-
270/
333
mW
T
A Temperature range - –40 85
°C
T
J Junction temperature range (range 6) –40 °C ≤ T
A
≤ 85 ° –40 105
1. It is recommended to power V
DD
and V
DDA
from the same source. A maximum difference of 300 mV between V
DD
and
V
DDA
can be tolerated during power-up and normal operation.
2. To sustain a voltage higher than V
DD
+0.3V, the internal pull-up/pull-down resistors must be disabled.
3. If T
A
is lower, higher P
D
values are allowed as long as T
J
does not exceed T
J
max (see Table 14: Thermal characteristics
on page 39).
Table 16. Embedded reset and power control block characteristics
Symbol Parameter Conditions Min Typ Max Unit
t
VDD
(1)
V
DD
rise time rate
BOR detector enabled 0 - ∞
µs/V
BOR detector disabled 0 - 1000
V
DD
fall time rate
BOR detector enabled 20 - ∞
BOR detector disabled 0 - 1000
T
RSTTEMPO
(1)
Reset temporization V
DD
rising, BOR enabled - 2 3.3 ms
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