Datasheet

DS12323 Rev 2 17/91
STM32L010F4/K4 Functional overview
28
3.3 Arm
®
Cortex
®
-M0+ core
The Cortex-M0+ processor is an entry-level 32-bit Arm Cortex processor designed for a
broad range of embedded applications. It offers significant benefits to developers, including:
• a simple architecture that is easy to learn and program
• ultra-low power, energy-efficient operation
• excellent code density
• deterministic, high-performance interrupt handling
• upward compatibility with Cortex-M processor family
• platform security robustness
The Cortex-M0+ processor is built on a highly area and power optimized 32-bit processor
core, with a 2-stage pipeline von Neumann architecture. The processor delivers exceptional
energy efficiency through a small but powerful instruction set and extensively optimized
design, providing high-end processing hardware including a single-cycle multiplier.
The Cortex-M0+ processor provides the exceptional performance expected of a modern 32-
bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers.
Owing to its embedded Arm core, the STM32L010F4/K4 are compatible with all Arm tools
and software.
Nested vectored interrupt controller (NVIC)
The ultra-low-power STM32L010F4/K4 embed a nested vectored interrupt controller, able to
handle up to 32 maskable interrupt channels and 4 priority levels.
The Cortex-M0+ processor closely integrates a configurable nested vectored interrupt
controller (NVIC), to deliver industry-leading interrupt performance.
The NVIC includes a non-maskable interrupt (NMI) and provides zero jitter interrupt option
plus four interrupt priority levels.
The tight integration of the processor core and NVIC provides fast execution of interrupt
service routines (ISRs), reducing the interrupt latency. This is achieved through the
hardware stacking of registers, and the ability to abandon and restart load-multiple and
store-multiple operations. Interrupt handlers do not require any assembler wrapper code,
removing any code overhead from the ISRs. Tail-chaining optimization also significantly
reduces the overhead when switching from one ISR to another.
To optimize low-power designs, the NVIC integrates sleep modes, such as a deep-sleep
function that enables the entire device to enter rapidly Stop or Standby mode.
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
GPIO
TIMx Timer input channel and trigger Y Y Y Y -
LPTIM1 Timer input channel and trigger Y Y Y Y Y
ADC Conversion trigger Y Y Y Y -
Table 4. STM32L010F4/K4 peripherals interconnect matrix (continued)
Interconnect
source
Inter-
connect
destination
Interconnect action Run Sleep
Low-
power
run
Low-
power
sleep
Stop
Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.Downloaded from Arrow.com.