Datasheet

DS12556 Rev 2 21/201
STM32H750VB STM32H750IB STM32H750XB Functional overview
48
The boot loader is located in non-user System memory. It is used to reprogram the Flash
memory through a serial interface (USART, I2C, SPI, USB-DFU). Refer to STM32
microcontroller System memory Boot mode application note (AN2606) for details.
3.5 Power supply management
3.5.1 Power supply scheme
STM32H750xB power supply voltages are the following:
• V
DD
= 1.62 to 3.6 V: external power supply for I/Os, provided externally through V
DD
pins.
• V
DDLDO
= 1.62 to 3.6 V: supply voltage for the internal regulator supplying V
CORE
• V
DDA
= 1.62 to 3.6 V: external analog power supplies for ADC, DAC, COMP and
OPAMP.
• V
DD33USB and
V
DD50USB
:
V
DD50USB
can be supplied through the USB cable to generate the V
DD33USB
via the
USB internal regulator. This allows supporting a V
DD
supply different from 3.3 V.
The USB regulator can be bypassed to supply directly V
DD33USB
if V
DD
= 3.3 V.
• V
BAT
= 1.2 to 3.6 V: power supply for the V
SW
domain when V
DD
is not present.
• V
CAP
: V
CORE
supply voltage, which values depend on voltage scaling (0.7 V, 0.9 V,
1.0 V, 1.1 V or 1.2 V). They are configured through VOS bits in PWR_D3CR register.
The V
CORE
domain is split into the following power domains that can be independently
switch off.
– D1 domain containing some peripherals and the Cortex
®
-M7 core.
– D2 domain containing a large part of the peripherals.
– D3 domain containing some peripherals and the system control.
During power-up and power-down phases, the following power sequence requirements
must be respected (see
Figure 2):
• When V
DD
is below 1 V, other power supplies (V
DDA
, V
DD33USB
, V
DD50USB
) must
remain below V
DD
+ 300 mV.
• When V
DD
is above 1 V, all power supplies are independent.
During the power-down phase, V
DD
can temporarily become lower than other supplies only
if the energy provided to the microcontroller remains below 1
mJ. This allows external
decoupling capacitors to be discharged with different time constants during the power-down
transient phase.
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