Datasheet

DS12556 Rev 2 149/201
STM32H750VB STM32H750IB STM32H750XB Electrical characteristics
189
Figure 32. Quad-SPI timing diagram - SDR mode
Figure 33. Quad-SPI timing diagram - DDR mode
Table 82. Quad SPI characteristics in DDR mode
(1)
Symbol Parameter Conditions Min Typ Max Unit
F
ck1/t(CK)
Quad-SPI clock
frequency
2.7 V<V
DD
<3.6 V
CL=20 pF
--100
MHz
1.62 V<V
DD
<3.6 V
CL=15 pF
--100
t
w(CKH)
Quad-SPI clock high and
low time
-
t
(CK)
/2 - 0.5 - t
(CK)
/2
ns
t
w(CKL)
t
(CK)
/2 - t
(CK)
/2+0.5
t
sr(IN)
, t
sf(IN)
Data input setup time - 2 - -
t
hr(IN)
, t
hf(IN)
Data input hold time - 2 - -
t
vr(OUT)
,
t
vf(OUT)
Data output valid time
DHHC=0 - 3.5 4
DHHC=1
Pres=1, 2...
-t
(CK)
/4+3.5 t
(CK)
/4+4
t
hr(OUT)
,
t
hf(OUT)
Data output hold time
DHHC=0 3 - -
DHHC=1
Pres=1, 2...
t
(CK)
/4+3 - -
1. Guaranteed by characterization results.
MSv36878V1
Data output
D0
D1 D2
Clock
Data input
D0 D1 D2
t
(CK)
t
w(CKH)
t
w(CKL)
t
r(CK)
t
f(CK)
t
s(IN)
t
h(IN)
t
v(OUT)
t
h(OUT)
MSv36879V1
Data output
D0
D2 D4
Clock
Data input
D0 D2 D4
t
(CK)
t
w(CKH)
t
w(CKL)
t
r(CK)
t
f(CK)
t
sf(IN)
t
hf(IN)
t
vf(OUT)
t
hr(OUT)
D1 D3 D5
D1 D3 D5
t
vr(OUT)
t
hf(OUT)
t
sr(IN)
t
hr(IN)
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