Datasheet

Electrical characteristics STM32H750VB STM32H750IB STM32H750XB
146/201 DS12556 Rev 2
Figure 31. SDRAM write access waveforms
Table 78. LPSDR SDRAM read timings
(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
t
W(SDCLK)
FMC_SDCLK period 2T
fmc_ker_ck
− 12T
fmc_ker_ck
+ 0.5
ns
t
su(SDCLKH_Data)
Data input setup time 2 -
t
h(SDCLKH_Data)
Data input hold time 1.5 -
t
d(SDCLKL_Add)
Address valid time - 2.5
t
d(SDCLKL_SDNE)
Chip select valid time - 2.5
t
h(SDCLKL_SDNE)
Chip select hold time 0 -
t
d(SDCLKL_SDNRAS
SDNRAS valid time - 0.5
t
h(SDCLKL_SDNRAS)
SDNRAS hold time 0 -
t
d(SDCLKL_SDNCAS)
SDNCAS valid time - 1.5
t
h(SDCLKL_SDNCAS)
SDNCAS hold time 0 -
MS32752V2
Row n Col1
FMC_SDCLK
FMC_A[12:0]
FMC_SDNRAS
FMC_SDNCAS
FMC_SDNWE
FMC_D[31:0]
FMC_SDNE[1:0]
td(SDCLKL_AddR)
td(SDCLKL_AddC)
th(SDCLKL_AddR)
th(SDCLKL_AddC)
td(SDCLKL_SNDE)
td(SDCLKL_Data)
th(SDCLKL_Data)
Col2 Coli Coln
Data2 Datai DatanData1
th(SDCLKL_SNDE)
td(SDCLKL_NRAS)
td(SDCLKL_NCAS)
th(SDCLKL_NCAS)
th(SDCLKL_NRAS)
td(SDCLKL_NWE) th(SDCLKL_NWE)
FMC_NBL[3:0]
td(SDCLKL_NBL)
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