Datasheet

DS12556 Rev 2 127/201
STM32H750VB STM32H750IB STM32H750XB Electrical characteristics
189
6.3.16 NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R
PU
(see Table 58: I/O static characteristics).
Unless otherwise specified, the parameters given in Table 62 are derived from tests
performed under the ambient temperature and V
DD
supply voltage conditions summarized
in
Table 22: General operating conditions.
Figure 17. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the V
IL(NRST)
max level specified in
Table 62. Otherwise the reset is not taken into account by the device.
Table 62. NRST pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
R
PU
(2)
Weak pull-up equivalent
resistor
(1)
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
V
IN
= V
SS
30 40 50
㏀
V
F(NRST)
(2)
2. Guaranteed by design.
NRST Input filtered pulse 1.71 V < V
DD
< 3.6 V - - 50
ns
V
NF(NRST)
(2)
NRST Input not filtered pulse
1.71 V < V
DD
< 3.6 V 300 - -
1.62 V < V
DD
< 3.6 V 1000 - -
ai14132d
STM32
R
PU
NRST
(2)
V
DD
Filter
Internal Reset
0.1 μF
External
reset circuit
(1)
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