Datasheet

Electrical characteristics STM32H750VB STM32H750IB STM32H750XB
124/201 DS12556 Rev 2
Output buffer timing characteristics (HSLV option disabled)
The HSLV bit of SYSCFG_CCCSR register can be used to optimize the I/O speed when the
product voltage is
below 2.5 V.
Table 60. Output timing characteristics (HSLV OFF)
(1)
Speed Symbol Parameter conditions Min Max Unit
00
F
max
(2)
Maximum frequency
C=50 pF, 2.7 V V
DD
3.6 V - 12
MHz
C=50 pF, 1.62 VV
DD
2.7 V - 3
C=30 pF, 2.7 VV
DD
3.6 V - 12
C=30 pF, 1.62 VV
DD
2.7 V - 3
C=10 pF, 2.7 VV
DD
3.6 V - 16
C=10 pF, 1.62 VV
DD
2.7 V - 4
t
r
/t
f
(3)
Output high to low level
fall time and output low
to high level rise time
C=50 pF, 2.7 V V
DD
3.6 V - 16.6
ns
C=50 pF, 1.62 VV
DD
2.7 V - 33.3
C=30 pF, 2.7 VV
DD
3.6 V - 13.3
C=30 pF, 1.62 VV
DD
2.7 V - 25
C=10 pF, 2.7 VV
DD
3.6 V - 10
C=10 pF, 1.62 VV
DD
2.7 V - 20
01
F
max
(2)
Maximum frequency
C=50 pF, 2.7 V V
DD
3.6 V - 60
MHz
C=50 pF, 1.62 VV
DD
2.7 V - 15
C=30 pF, 2.7 VV
DD
3.6 V - 80
C=30 pF, 1.62 VV
DD
2.7 V - 15
C=10 pF, 2.7 VV
DD
3.6 V - 110
C=10 pF, 1.62 VV
DD
2.7 V - 20
t
r
/t
f
(3)
Output high to low level
fall time and output low
to high level rise time
C=50 pF, 2.7 V V
DD
3.6 V - 5.2
ns
C=50 pF, 1.62 VV
DD
2.7 V - 10
C=30 pF, 2.7 VV
DD
3.6 V - 4.2
C=30 pF, 1.62 VV
DD
2.7 V - 7.5
C=10 pF, 2.7 VV
DD
3.6 V - 2.8
C=10 pF, 1.62 VV
DD
2.7 V - 5.2
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