Datasheet

ManualsBrandsST ManualsEmbedded Processors & ControllersMicrocontroller 32bit 128KB LQFP

This is information on a product in full production.

June 2018 DS12556 Rev 2 1/201

STM32H750VB STM32H750IB

STM32H750XB

32-bit Arm

Cortex

-M7 400MHz MCUs, 128 KB Flash,

1MB RAM, 46 com. and analog interfaces, crypto

Datasheet - production data

Features

Core

• 32-bit Arm

Cortex

-M7 core with double-

precision FPU and L1 cache: 16 Kbytes of data

and 16 Kbytes of instruction cache; frequency

up to 400 MHz, MPU, 856 DMIPS/

2.14 DMIPS/MHz (Dhrystone 2.1), and DSP

instructions

Memories

• 128 Kbytes of Flash memory

• 1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc.

64 Kbytes of ITCM RAM + 128 Kbytes of

DTCM RAM for time critical routines),

864 Kbytes of user SRAM, and 4 Kbytes of

SRAM in Backup domain

• Dual mode Quad-SPI memory interface

running up to 133 MHz

• Flexible external memory controller with up to

32-bit data bus:

– SRAM, PSRAM, NOR Flash memory

clocked up to 133 MHz in synchronous

mode

– SDRAM/LPSDR SDRAM

– 8/16-bit NAND Flash memories

• CRC calculation unit

Security

• ROP, PC-ROP, active tamper, secure firmware

upgrade support, Secure access mode

General-purpose input/outputs

• Up to 168 I/O ports with interrupt capability

Reset and power management

• 3 separate power domains which can be

independently clock-gated or switched off:

– D1: high-performance capabilities

– D2: communication peripherals and timers

– D3: reset/clock control/power management

• 1.62 to 3.6 V application supply and I/Os

• POR, PDR, PVD and BOR

• Dedicated USB power embedding a 3.3 V

internal regulator to supply the internal PHYs

• Embedded regulator (LDO) with configurable

scalable output to supply the digital circuitry

• Voltage scaling in Run and Stop mode (5

configurable ranges)

• Backup regulator (~0.9 V)

• Voltage reference for analog peripheral/V

REF+

• Low-power modes: Sleep, Stop, Standby and

BAT

supporting battery charging

Low-power consumption

• Total current consumption down to 4

µA

Clock management

• Internal oscillators: 64 MHz HSI, 48 MHz

HSI48, 4 MHz CSI, 32 kHz LSI

• External oscillators: 4-48 MHz HSE,

32.768 kHz LSE

• 3× PLLs (1 for the system clock, 2 for kernel

clocks) with Fractional mode

FBGA

LQFP100

(14x14 mm)

UFBGA176+25

(10x10 mm)

FBGA

TFBGA240+25 (14x14 mm)

www.st.com

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Summary of content (201 pages)

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STM32H750VB STM32H750IB STM32H750XB 32-bit Arm® Cortex®-M7 400MHz MCUs, 128 KB Flash, 1MB RAM, 46 com. and analog interfaces, crypto Datasheet - production data Features FBGA Core • 32-bit Arm® Cortex®-M7 core with doubleprecision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction cache; frequency up to 400 MHz, MPU, 856 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.
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STM32H750VB STM32H750IB STM32H750XB • Chrom-ART graphical hardware Accelerator™ (DMA2D) to reduce CPU load Interconnect matrix • 3 bus matrices (1 AXI and 2 AHB) • Bridges (5× AHB2-APB, 2× AXI2-AHB) • Hardware JPEG Codec 4 DMA controllers to unload the CPU Up to 22 timers and watchdogs • 1× high-speed master direct memory access controller (MDMA) with linked list support • 1× high-resolution timer (2.
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STM32H750VB STM32H750IB STM32H750XB Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 Arm® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.
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Contents 4/201 Downloaded from Arrow.com. STM32H750VB STM32H750IB STM32H750XB 3.20 Digital-to-analog converters (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.21 Ultra-low-power comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.22 Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.23 Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 32 3.
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STM32H750VB STM32H750IB STM32H750XB Contents 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.1.
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Contents 7 STM32H750VB STM32H750IB STM32H750XB 6.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 6.3.24 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 6.3.25 Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 6.3.26 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 6.3.
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STM32H750VB STM32H750IB STM32H750XB List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44.
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List of tables Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93.
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STM32H750VB STM32H750IB STM32H750XB Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. List of tables DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 LTDC characteristics . . . . . . . . . . . . .
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List of figures STM32H750VB STM32H750IB STM32H750XB List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41.
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STM32H750VB STM32H750IB STM32H750XB Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. List of figures SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 MDIO Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 SDIO high-speed mode .
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Introduction 1 STM32H750VB STM32H750IB STM32H750XB Introduction This document provides information on STM32H750xB microcontrollers, such as description, functional overview, pin assignment and definition, electrical characteristics, packaging, and ordering information. This document should be read in conjunction with the STM32H750xB reference manual (RM0433), available from the STMicroelectronics website www.st.com.
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STM32H750VB STM32H750IB STM32H750XB 2 Description Description STM32H750xB devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC core operating at up to 400 MHz. The Cortex® -M7 core features a floating point unit (FPU) which supports Arm® double-precision (IEEE 754 compliant) and single-precision dataprocessing instructions and data types. STM32H750xB devices support a full set of DSP instructions and a memory protection unit (MPU) to enhance application security.
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Description STM32H750VB STM32H750IB STM32H750XB STM32H750xB devices operate in the –40 to +85 °C temperature range from a 1.62 to 3.6 V power supply. The supply voltage can drop down to 1.62 V by using an external power supervisor (see Section 3.5.2: Power supply supervisor) and connecting the PDR_ON pin to VSS. Otherwise the supply voltage must stay above 1.71 V with the embedded power voltage detector enabled.
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STM32H750VB STM32H750IB STM32H750XB Description Table 1.
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Description STM32H750VB STM32H750IB STM32H750XB Table 1. STM32H750xB features and peripheral counts (continued) Peripherals STM32H750VB Operating temperatures Package STM32H750IB STM32H750XB Ambient temperatures: –40 up to +85 °C(4) Junction temperature: –40 to + 125 °C LQFP100 UFBGA176+25 TFBGA240+25 1. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. 2.
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STM32H750VB STM32H750IB STM32H750XB Description Figure 1.
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Functional overview STM32H750VB STM32H750IB STM32H750XB 3 Functional overview 3.1 Arm® Cortex®-M7 with FPU The Arm® Cortex®-M7 with double-precision FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and optimized power consumption, while delivering outstanding computational performance and low interrupt latency.
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STM32H750VB STM32H750IB STM32H750XB 3.3 Memories 3.3.1 Embedded Flash memory Functional overview The STM32H750xB devices embed 128 Kbytes of Flash memory that can be used for storing programs and data. The Flash memory is organized as follows: 3.3.
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Functional overview 3.3.3 STM32H750VB STM32H750IB STM32H750XB Embedded SRAM All devices feature: • 512 Kbytes of AXI-SRAM mapped onto AXI bus on D1 domain. • SRAM1 mapped on D2 domain: 128 Kbytes • SRAM2 mapped on D2 domain: 128 Kbytes • SRAM3 mapped on D2 domain: 32 Kbytes • SRAM4 mapped on D3 domain: 64 Kbytes • 4 Kbytes of backup SRAM The content of this area is protected against possible unwanted write accesses, and is retained in Standby or VBAT mode.
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STM32H750VB STM32H750IB STM32H750XB Functional overview The boot loader is located in non-user System memory. It is used to reprogram the Flash memory through a serial interface (USART, I2C, SPI, USB-DFU). Refer to STM32 microcontroller System memory Boot mode application note (AN2606) for details. 3.5 Power supply management 3.5.1 Power supply scheme STM32H750xB power supply voltages are the following: • VDD = 1.62 to 3.6 V: external power supply for I/Os, provided externally through VDD pins.
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Functional overview STM32H750VB STM32H750IB STM32H750XB Figure 2. Power-up/power-down sequence V 3.6 VDDX(1) VDD VBOR0 1 0.3 Power-on Invalid supply area Operating mode VDDX < VDD + 300 mV Power-down VDDX independent from VDD time MSv47490V1 1. VDDx refers to any power supply among VDDA, VDD33USB, VDD50USB. 3.5.
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STM32H750VB STM32H750IB STM32H750XB 3.5.3 Functional overview Voltage regulator The same voltage regulator supplies the 3 power domains (D1, D2 and D3). D1 and D2 can be independently switched off.
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Functional overview STM32H750VB STM32H750IB STM32H750XB Table 2. System vs domain low-power mode D1 domain power mode System power mode Run 3.7 D2 domain power mode D3 domain power mode DRun/DStop/DStandby DRun/DStop/DStandby DRun Stop DStop/DStandby DStop/DStandby DStop Standby DStandby DStandby DStandby Reset and clock controller (RCC) The clock and reset controller is located in D3 domain.
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STM32H750VB STM32H750IB STM32H750XB 3.7.2 Functional overview System reset sources Power-on reset initializes all registers while system reset reinitializes the system except for the debug, part of the RCC and power controller status registers, as well as the backup power domain. A system reset is generated in the following cases: 3.
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DS12556 Rev 2 MDMA DMA2D Slave interface Bus multiplexer LTDC Master interface TCM AHB AXI APB 64-bit AXI bus matrix D1 domain SDMMC1 DTCM 128 Kbyte ITCM 64 Kbyte 64-bit bus 32-bit bus AXIM I$ D$ 16KB 16KB D2-to-D1 AHB Legend CPU AHBP Cortex-M7 D1-to-D3 AHB FMC QSPI AXI SRAM 512 Kbyte Flash memory 128 Kbytes BDMA Backup SRAM 4 Kbyte SRAM4 64 Kbyte AHB4 APB4 32-bit AHB bus matrix D3 domain D2-to-D3 AHB APB2 APB1 AHB2 AHB1 SRAM3 32 Kbyte SRAM2 128 Kbyte AHB3 USBHS2 SRA
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STM32H750VB STM32H750IB STM32H750XB 3.10 Functional overview DMA controllers . The devices feature four DMA instances to unload CPU activity: • A master direct memory access (MDMA) The MDMA is a high-speed DMA controller, which is in charge of all types of memory transfers (peripheral to memory, memory to memory, memory to peripheral), without any CPU action. It features a master AXI interface and a dedicated AHB interface to access Cortex®-M7 TCM memories. The MDMA is located in D1 domain.
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Functional overview 3.12 STM32H750VB STM32H750IB STM32H750XB Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller which is able to manage 16 priority levels, and handle up to 150 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-M7 with FPU core.
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STM32H750VB STM32H750IB STM32H750XB 3.15 Functional overview Flexible memory controller (FMC) The FMC controller main features are the following: • Interface with static-memory mapped devices including: 3.
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Functional overview STM32H750VB STM32H750IB STM32H750XB In addition, an analog watchdog feature can accurately monitor the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1, TIM2, TIM3, TIM4, TIM6, TIM8, TIM15, HRTIM1 and LPTIM1 timer. 3.
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STM32H750VB STM32H750IB STM32H750XB 3.20 Functional overview Digital-to-analog converters (DAC) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs.
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Functional overview STM32H750VB STM32H750IB STM32H750XB The devices embeds two operational amplifiers (OPAMP1 and OPAMP2) with two inputs and one output each. These three I/Os can be connected to the external pins, thus enabling any type of external interconnections. The operational amplifiers can be configured internally as a follower, as an amplifier with a non-inverting gain ranging from 2 to 16 or with inverting gain ranging from -1 to -15. 3.
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STM32H750VB STM32H750IB STM32H750XB • Functional overview short circuit detector to detect saturated analog input values (bottom and top range): – up to 8-bit counter to detect 1..
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Functional overview 3.25 STM32H750VB STM32H750IB STM32H750XB LCD-TFT controller The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue) and delivers all signals to interface directly to a broad range of LCD and TFT panels up to XGA (1024x768) resolution with the following features: 3.
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STM32H750VB STM32H750IB STM32H750XB 3.
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Functional overview STM32H750VB STM32H750IB STM32H750XB Table 4.
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STM32H750VB STM32H750IB STM32H750XB 3.29.1 Functional overview High-resolution timer (HRTIM1) The high-resolution timer (HRTIM1) allows generating digital signals with high-accuracy timings, such as PWM or phase-shifted pulses. It consists of 6 timers, 1 master and 5 slaves, totaling 10 high-resolution outputs, which can be coupled by pairs for deadtime insertion.
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Functional overview 3.29.2 STM32H750VB STM32H750IB STM32H750XB Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers.
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STM32H750VB STM32H750IB STM32H750XB 3.29.4 Functional overview Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base. TIM6 and TIM7 support independent DMA request generation. 3.29.5 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) The low-power timers have an independent clock and is running also in Stop mode if it is clocked by LSE, LSI or an external clock.
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Functional overview 3.30 STM32H750VB STM32H750IB STM32H750XB Real-time clock (RTC), backup SRAM and backup registers The RTC is an independent BCD timer/counter. It supports the following features: • Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format. • Automatic correction for 28, 29 (leap year), 30, and 31 days of the month. • Two programmable alarms. • On-the-fly correction from 1 to 32767 RTC clock pulses.
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STM32H750VB STM32H750IB STM32H750XB 3.31 Functional overview Inter-integrated circuit interface (I2C) STM32H750xB devices embed four I2C interfaces. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: • • 3.32 I2C-bus specification and user manual rev.
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Functional overview STM32H750VB STM32H750IB STM32H750XB All USART have a clock domain independent from the CPU clock, allowing the USARTx to wake up the MCU from Stop mode.The wakeup from Stop mode is programmable and can be done on: • Start bit detection • Any received data frame • A specific programmed data frame • Specific TXFIFO/RXFIFO status when FIFO mode is enabled. All USART interfaces can be served by the DMA controller. Table 5.
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STM32H750VB STM32H750IB STM32H750XB Functional overview The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode. The wakeup from Stop mode are programmable and can be done on: • Start bit detection • Any received data frame • A specific programmed data frame • Specific TXFIFO/RXFIFO status when FIFO mode is enabled. Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud.
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Functional overview 3.36 STM32H750VB STM32H750IB STM32H750XB SPDIFRX Receiver Interface (SPDIFRX) The SPDIFRX peripheral is designed to receive an S/PDIF flow compliant with IEC-60958 and IEC-61937. These standards support simple stereo streams up to high sample rate, and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up to 5.1). The main SPDIFRX features are the following: • Up to 4 inputs available • Automatic symbol rate detection • Maximum symbol rate: 12.
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STM32H750VB STM32H750IB STM32H750XB 3.38 Functional overview Management Data Input/Output (MDIO) slaves The devices embed an MDIO slave interface it includes the following features: • – 32 x 16-bit firmware read/write, MDIO read-only output data registers – 32 x 16-bit firmware read-only, MDIO write-only input data registers • Configurable slave (port) address • Independently maskable interrupts/events: • 3.
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Functional overview 3.41 STM32H750VB STM32H750IB STM32H750XB Universal serial bus on-the-go high-speed (OTG_HS) The devices embed two USB OTG high-speed (up to 480 Mbit/s) device/host/OTG peripheral. OTG-HS1 supports both full-speed and high-speed operations, while OTG-HS2 supports only full-speed operations. They both integrate the transceivers for full-speed operation (12 Mbit/s) and are able to operate from the internal HSI48 oscillator.
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STM32H750VB STM32H750IB STM32H750XB Functional overview The devices include the following features: 3.
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Memory mapping 4 STM32H750VB STM32H750IB STM32H750XB Memory mapping Refer to the product line reference manual for details on the memory mapping as well as the boundary addresses for all peripherals. 48/201 Downloaded from Arrow.com.
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STM32H750VB STM32H750IB STM32H750XB 5 Pin descriptions Pin descriptions PA14 PA15 PC10 PC11 PC12 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PB3 PB4 PB5 PB6 PB7 BOOT0 PB8 PB9 PE0 PE1 VSS VDD Figure 4.
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Pin descriptions STM32H750VB STM32H750IB STM32H750XB Figure 5.
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STM32H750VB STM32H750IB STM32H750XB Pin descriptions Figure 6.
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Pin descriptions STM32H750VB STM32H750IB STM32H750XB Table 6. Legend/abbreviations used in the pinout table Name Pin name Pin type Abbreviation Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin I/O Input / output pin ANA Analog-only Input FT 5 V tolerant I/O TT 3.3 V tolerant I/O B Dedicated BOOT0 pin RST I/O structure Notes Pin functions 52/201 Downloaded from Arrow.com.
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STM32H750VB STM32H750IB STM32H750XB Pin descriptions Table 7.
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Pin descriptions STM32H750VB STM32H750IB STM32H750XB Table 7.
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STM32H750VB STM32H750IB STM32H750XB Pin descriptions Table 7.
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Pin descriptions STM32H750VB STM32H750IB STM32H750XB Table 7.
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STM32H750VB STM32H750IB STM32H750XB Pin descriptions Table 7.
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Pin descriptions STM32H750VB STM32H750IB STM32H750XB Table 7.
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STM32H750VB STM32H750IB STM32H750XB Pin descriptions Table 7.
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Pin descriptions STM32H750VB STM32H750IB STM32H750XB Table 7.
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STM32H750VB STM32H750IB STM32H750XB Pin descriptions Table 7.
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Pin descriptions STM32H750VB STM32H750IB STM32H750XB Table 7.
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STM32H750VB STM32H750IB STM32H750XB Pin descriptions Table 7.
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Pin descriptions STM32H750VB STM32H750IB STM32H750XB Table 7.
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STM32H750VB STM32H750IB STM32H750XB Pin descriptions Table 7.
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Pin descriptions STM32H750VB STM32H750IB STM32H750XB Table 7.
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STM32H750VB STM32H750IB STM32H750XB Pin descriptions Table 7.
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Pin descriptions STM32H750VB STM32H750IB STM32H750XB Table 7.
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STM32H750VB STM32H750IB STM32H750XB Pin descriptions Table 7.
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Pin descriptions STM32H750VB STM32H750IB STM32H750XB Table 7.
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STM32H750VB STM32H750IB STM32H750XB Pin descriptions Table 7. STM32H750xB pin/ball definition (continued) LQFP100 UFBGA176+25 TFBGA240 +25 Pin name (function after reset) Pin type I/O structure Notes Pin/ball name Alternate functions - H9 - VSS S - - - - - K9 - VSS S - - - - - K10 - VSS S - - - - Additional functions 1. When this pin/ball was previously configured as an oscillator, the oscillator function is kept during and after a reset.
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DS12556 Rev 2 NJTRST - - - - PB5 PB6 PB7 PB8 TIM2_CH2 JTDO/TRA CESWO PB3 PB4 - - PB2 TIM4_CH1 TIM4_CH2 TIM16_CH1 N TIM17_CH1 N TIM4_CH3 TIM3_CH2 TIM17_ BKIN TIM16_CH1 TIM3_CH1 HRTIM_ FLT4 SAI1_D1 TIM3_CH4 TIM3_CH3 SAI1/TIM3/ 4/5/12/ HRTIM1 TIM16_ BKIN TIM1_CH3N - PB1 TIM1_CH2N - PB0 SYS TIM1/2/16/1 7/LPTIM1/ HRTIM1 AF1 AF0 Port HRTIM_ FLT1 TIM2_CH1/ TIM2_ETR JTDI PA15 AF2 - - JTCKSWCLK PA14 SAI1/TIM3/ 4/5/12/ HRTIM1 AF2 SYS AF1 TIM1/2/16/1 7/LPTIM1/ HR
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Electrical characteristics 6 STM32H750VB STM32H750IB STM32H750XB Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.
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STM32H750VB STM32H750IB STM32H750XB 6.1.6 Electrical characteristics Power supply scheme VDD33USB 100 nF 100 nF Figure 9. Power supply scheme VDD33USB USB IOs USB regulator VDDLDO VCAP Level shifter IOs N(1) x 100 nF + 1 x 4.
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Electrical characteristics 6.1.7 STM32H750VB STM32H750IB STM32H750XB Current consumption measurement Figure 10. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 19: Voltage characteristics, Table 20: Current characteristics, and Table 21: Thermal characteristics may cause permanent damage to the device.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Table 20.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB 6.3 Operating conditions 6.3.1 General operating conditions Table 22. General operating conditions Symbol Parameter Operating conditions Min Max (1) 3.6 VDD Standard operating voltage - VDDLDO Supply voltage for the internal regulator VDDLDO ≤ VDD 1.62(1) 3.6 USB used 3.0 3.6 USB not used 0 3.6 ADC or COMP used 1.62 DAC used 1.8 OPAMP used 2.0 VREFBUF used 1.
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STM32H750VB STM32H750IB STM32H750XB 6.3.2 Electrical characteristics VCAP external capacitor Stabilization for the main regulator is achieved by connecting an external capacitor CEXT to the VCAP pin. CEXT is specified in Table 23. Two external capacitors can be connected to VCAP pins. Figure 11. External capacitor CEXT C ESR R Leak MS19044V2 1. Legend: ESR is the equivalent series resistance. Table 23.
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Electrical characteristics 6.3.4 STM32H750VB STM32H750IB STM32H750XB Embedded reset and power control block characteristics The parameters given in Table 25 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 22: General operating conditions. Table 25.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Table 25. Reset and power control block characteristics (continued) Symbol Parameter Conditions Min Typ Max VAVM_0 Analog voltage detector for VDDA threshold 0 Rising edge 1.66 1.71 1.76 1.56 1.61 1.66 VAVM_1 Analog voltage detector for VDDA threshold 1 Rising edge 2.06 2.12 2.19 1.96 2.02 2.08 VAVM_2 Analog voltage detector for VDDA threshold 2 Rising edge 2.42 2.50 2.58 2.35 2.42 2.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB Table 26. Embedded reference voltage (continued) Symbol Parameter Conditions Min Typ Max VREFINT_DIV1 1/4 reference voltage - - 25 - VREFINT_DIV2 1/2 reference voltage - - 50 - VREFINT_DIV3 3/4 reference voltage - - 75 - 1. The shortest sampling time for the application can be determined by multiple iterations. 2. Guaranteed by design. Unit % VREFINT Table 27.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Table 28.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB Table 29.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Table 31. Typical consumption in Run mode and corresponding performance versus code position Symbol Parameter Conditions All peripherals disabled, cache ON Supply current in Run mode IDD Code frcc_c_ck (MHz) CoreMark Typ ITCM 400 2012 71 35 FLASH A 400 2012 105 52 AXI SRAM 400 2012 105 52 SRAM1 400 2012 105 52 SRAM4 400 2012 105 ITCM 400 2012 71 FLASH A 400 593 70.5 119 AXI SRAM 400 344 70.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB Table 34. Typical and maximum current consumption in Stop mode, regulator ON Max(1) Symbol Parameter Flash memory in low-power mode, no IWDG D1Stop, D2Stop, D3Stop IDD(Stop) Conditions Flash memory ON, no IWDG D1Stop, D2Standby, D3Stop Flash memory OFF, no IWDG Flash memory ON, no IWDG D1Standby, D2Stop, D3Stop Flash OFF, no IWDG D1Standby, D2Standby, D3Stop Typ TJ = 25°C TJ = 85°C TJ = 105°C TJ = 125°C SVOS5 1.4 7.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Table 36. Typical and maximum current consumption in VBAT mode Typ(1) Conditions Symbol IDD (VBAT) Parameter Supply current in standby mode Backup SRAM RTC & LSE 1.2 V OFF OFF 0.024 ON OFF 1.4 1.6 1.8 OFF ON 0.24 0.45 ON ON 1.97 2.37 Max (3 V) TJ = 25°C TJ = 85°C 0.035 0.062 0.096 0.5(1) 4.1(1) 10(1) 24(1) 1.8 4.4(1) 22(1) 48(1) 87(1) 0.62 0.73 - - - - 2.57 2.77 - - - - 2V 3V 3.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. On-chip peripheral current consumption The MCU is placed under the following conditions: • At startup, all I/O pins are in analog input configuration. • All peripherals are disabled unless otherwise mentioned. • The I/O compensation cell is enabled. • frcc_c_ck is the CPU clock. fPCLK = frcc_c_ck/4, and fHCLK = frcc_c_ck/2.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Table 37. Peripheral current consumption in Run mode IDD(Typ) Peripheral AHB3 Unit VOS1 VOS2 VOS3 MDMA 8.3 7.6 7 DMA2D 21 20 18 JPEG 24 23 21 FLASH 9.9 9 8.3 FMC registers 0.9 0.9 0.8 FMC kernel 6.1 5.5 5.3 QUADSPI registers 1.5 1.4 1.3 QUADSPI kernel 0.9 0.8 0.7 SDMMC1 registers 8 7.2 6.8 SDMMC1 kernel 2.4 2 1.8 DTCM1 5.7 5 4.5 DTCM2 5.5 4.8 4.3 ITCM 3.2 2.9 2.6 D1SRAM1 7.6 6.8 6.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB Table 37. Peripheral current consumption in Run mode (continued) IDD(Typ) Peripheral AHB2 AHB4 APB3 102/201 Downloaded from Arrow.com. Unit VOS1 VOS2 VOS3 DCMI 1.7 1.7 1.7 CRYPT 0.1 0.1 0.1 HASH 0.1 0.1 0.1 RNG registers 1.8 1.4 1.2 RNG kernel - 9.6 9.6 SDMMC2 registers 13 12 11 SDMMC2 kernel 2.7 2.5 2.4 D2SRAM1 3.3 3.1 2.8 D2SRAM2 2.9 2.7 2.5 D2SRAM3 1.9 1.8 1.7 Bridge AHB2 0.1 0.1 0.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Table 37. Peripheral current consumption in Run mode (continued) IDD(Typ) Peripheral APB1 Unit VOS1 VOS2 VOS3 TIM2 3.5 3.2 2.9 TIM3 3.4 3.1 2.7 TIM4 2.7 2.5 1.9 TIM5 3.2 2.9 2.5 TIM6 1 0.8 0.7 TIM7 1 0.9 0.7 TIM12 1.7 1.5 1.2 TIM13 1.5 1.3 1 TIM14 1.4 1.3 0.9 LPTIM1 registers 0.7 0.6 0.5 LPTIM1 kernel 2.3 2.1 1.9 WWDG2 0.6 0.4 0.4 SPI2 registers 1.8 1.5 1.2 SPI2 kernel 0.6 0.5 0.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB Table 37. Peripheral current consumption in Run mode (continued) IDD(Typ) Peripheral APB1 (continued) 104/201 Downloaded from Arrow.com. Unit VOS1 VOS2 VOS3 UART5 registers 1.4 1.4 1 UART5 kernel 3.6 3.2 3.1 I2C1 registers 0.8 0.8 0.6 I2C1 kernel 2 1.8 1.7 I2C2 registers 0.7 0.7 0.4 I2C2 kernel 1.9 1.7 1.6 I2C3 registers 0.9 0.7 0.6 I2C3 kernel 2.1 1.9 1.9 HDMI-CEC registers 0.5 0.3 0.3 DAC1/2 1.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Table 37. Peripheral current consumption in Run mode (continued) IDD(Typ) Peripheral APB2 Unit VOS1 VOS2 VOS3 TIM1 5.1 4.8 4.3 TIM8 5.4 4.9 4.6 USART1 registers 2.7 2.6 2.5 USART1 kernel 0.1 0.1 0.1 USART6 registers 2.6 2.5 2.5 USART6 kernel 0.1 0.1 0.1 SPI1 registers 1.8 1.6 1.6 SPI1 kernel 1 0.8 0.6 SPI4 registers 1.6 1.5 1.5 SPI4 kernel 0.5 0.4 0.4 TIM15 3.1 2.8 2.7 TIM16 2.4 2.1 2.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB Table 37. Peripheral current consumption in Run mode (continued) IDD(Typ) Peripheral APB4 Unit VOS1 VOS2 VOS3 SYSCFG 1 0.7 0.7 LPUART1 registers 1.1 1.1 1.1 LPUART1 kernel 2.6 2.4 2.1 SPI6 registers 1.6 1.5 1.4 SPI6 kernel 0.2 0.2 0.2 I2C4 registers 0.1 0.1 0.1 I2C4 kernel 2.4 2.1 2 LPTIM2 registers 0.5 0.5 0.5 LPTIM2 kernel 2.3 2.1 1.8 LPTIM3 registers 0.5 0.5 0.5 LPTIM3 kernel 2 2.1 1.
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STM32H750VB STM32H750IB STM32H750XB 6.3.7 Electrical characteristics Wakeup time from low-power modes The wakeup times given in Table 39 are measured starting from the wakeup event trigger up to the first instruction executed by the CPU: • For Stop or Sleep modes: the wakeup event is WFE. • WKUP (PC1) pin is used to wakeup from Standby, Stop and Sleep modes. All timings are derived from tests performed under ambient temperature and VDD=3.3 V. Table 39.
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Electrical characteristics 6.3.8 STM32H750VB STM32H750IB STM32H750XB External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The external clock signal has to respect the Table 58: I/O static characteristics. However, the recommended clock input waveform is shown in Figure 12. Table 40.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The external clock signal has to respect the Table 58: I/O static characteristics. However, the recommended clock input waveform is shown in Figure 13. Table 41.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 42.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Figure 14. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 8 MHz resonator CL2 fHSE OSC_IN REXT(1) RF Bias controlled gain OSC_OU T STM32 ai17530b 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator.
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Electrical characteristics Note: STM32H750VB STM32H750IB STM32H750XB For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 15. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 fLSE OSC32_IN Bias RF controlled gain 32.768 kH z resonator OSC32_OU T CL2 STM32 ai17531b 1.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics 5. Jitter measurements are performed without clock source activated in parallel. 64 MHz high-speed internal RC oscillator (HSI) Table 45. HSI oscillator characteristics(1) Symbol Parameter HSI frequency fHSI TRIM HSI user trimming step DuCy(HSI) Duty Cycle ΔVDD (HSI) HSI oscillator frequency drift over VDD (reference is 3.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB Table 46. CSI oscillator characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit tstab(CSI) CSI oscillator stabilization time (to reach ±3% of fCSI) - - - 4 cycle IDD(CSI) CSI oscillator power consumption - - 23 30 µA Min Typ Max Unit VDD = 3.3 V, TJ = 25 °C (after calibration) 31.4 32 32.6 TJ = –40 to 105 °C, VDD = 1.62 to 3.6 V 29.76 - 33.60 1. Guaranteed by design. 2.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Table 48. PLL characteristics (wide VCO frequency range)(1) (continued) Symbol tLOCK Parameter PLL lock time Cycle-to-cycle jitter Jitter Long term jitter IDD(PLL)(3) Conditions Typ Max (3) Unit (3) 150 Normal mode - 50 Sigma-delta mode (CKIN ≥ 8 MHz) - 58(3) 166(3) VCO = 192 MHz - 134 - VCO = 200 MHz - 134 - VCO = 400 MHz - 76 - VCO = 800 MHz - 39 - Normal mode - ±0.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB Table 49.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Table 51. Flash memory programming Symbol tprog tERASE128KB tME Min(1) Typ Max(1) Program/erase parallelism x 8 - 290 580(2) Program/erase parallelism x 16 - 180 360 Program/erase parallelism x 32 - 130 260 Program/erase parallelism x 64 - 100 200 Program/erase parallelism x 8 - 2 4 Program/erase parallelism x 16 - 1.8 3.
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Electrical characteristics 6.3.12 STM32H750VB STM32H750IB STM32H750XB EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB Static latchup Two complementary static tests are required on six parts to assess the latchup performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with JESD78 IC latchup standard. Table 56. Electrical sensitivities Symbol LU 6.3.
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STM32H750VB STM32H750IB STM32H750XB 6.3.15 Electrical characteristics I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 58: I/O static characteristics are derived from tests performed under the conditions summarized in Table 22: General operating conditions. All I/Os are CMOS and TTL compliant (except for BOOT0). Table 58. I/O static characteristics Symbol Parameter Condition Min Typ Max - - 0.3xVDD - - 0.4xVDD− 0.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB Figure 16. VIL/VIH for all I/Os except BOOT0 3 2.5 2 S req Voltage CMO TLL requirement: VIHmin = 2 V 0.7V D in= t: V IHm en uirem D +0.25 =0.47VDD on VIHmin ulati d on sim 1.5 Base +0.1 =0.4VDD max lation VIL n simu V DD o .3 d 0 e = s Ba max ment: VIL require CMOS TLL requirement: VILmin = 0.8 V 1 0.5 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Output voltage levels Unless otherwise specified, the parameters given in Table 59 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 22: General operating conditions. All I/Os are CMOS and TTL compliant. Table 59. Output voltage characteristics(1) Symbol Parameter Conditions(3) Min Max Unit port(2) Output low level voltage CMOS IIO=8 mA 2.7 V≤ VDD ≤3.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB Output buffer timing characteristics (HSLV option disabled) The HSLV bit of SYSCFG_CCCSR register can be used to optimize the I/O speed when the product voltage is below 2.5 V. Table 60. Output timing characteristics (HSLV OFF)(1) Speed Symbol Fmax(2) Parameter Maximum frequency 00 tr/tf(3) Fmax(2) Output high to low level fall time and output low to high level rise time Maximum frequency 01 tr/tf(3) 124/201 Downloaded from Arrow.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Table 60. Output timing characteristics (HSLV OFF)(1) (continued) Speed Symbol Parameter conditions Min Max C=50 pF, 2.7 V≤VDD≤3.6 V - 85 C=50 pF, 1.62 V≤VDD≤2.7 V(4) - 35 - 110 C=30 pF, 1.62 V≤VDD≤2.7 V - 40 C=10 pF, 2.7 V≤VDD≤3.6 V(4) - 166 C=10 pF, 1.62 V≤VDD≤2.7 V(4) - 100 - 3.8 (4) (4) Fmax(2) Maximum frequency 10 C=30 pF, 2.7 V≤VDD≤3.6 V (4) (4) C=50 pF, 2.7 V≤VDD≤3.6 V (4) C=50 pF, 1.62 V≤VDD≤2.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB Output buffer timing characteristics (HSLV option enabled) Table 61.
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STM32H750VB STM32H750IB STM32H750XB 6.3.16 Electrical characteristics NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 58: I/O static characteristics). Unless otherwise specified, the parameters given in Table 62 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 22: General operating conditions. Table 62.
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Electrical characteristics 6.3.17 STM32H750VB STM32H750IB STM32H750XB FMC characteristics Unless otherwise specified, the parameters given in Table 63 to Table 76 for the FMC interface are derived from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage conditions summarized in Table 22: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Measurement points are done at CMOS levels: 0.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Figure 18. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms tw(NE) FMC_NE tv(NOE_NE) t w(NOE) t h(NE_NOE) FMC_NOE FMC_NWE tv(A_NE) FMC_A[25:0] t h(A_NOE) Address tv(BL_NE) t h(BL_NOE) FMC_NBL[1:0] t h(Data_NE) t su(Data_NOE) th(Data_NOE) t su(Data_NE) Data FMC_D[15:0] t v(NADV_NE) tw(NADV) FMC_NADV (1) FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE) MS32753V1 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB Table 63. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) Symbol Min Max 2Tfmc_ker_ck − 1 2 Tfmc_ker_ck +1 0 0.5 2Tfmc_ker_ck − 1 2Tfmc_ker_ck + 1 FMC_NOE high to FMC_NE high hold time 0 - FMC_NEx low to FMC_A valid - 0.5 th(A_NOE) Address hold time after FMC_NOE high 0 - tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Figure 19. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms tw(NE) FMC_NEx FMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FMC_NWE tv(A_NE) FMC_A[25:0] th(A_NWE) Address tv(BL_NE) FMC_NBL[1:0] th(BL_NWE) NBL tv(Data_NE) th(Data_NWE) Data FMC_D[15:0] t v(NADV_NE) tw(NADV) FMC_NADV (1) FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE) MS32754V1 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. Table 65.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB Table 66. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings(1)(2) Symbol Min Max 8Tfmc_ker_ck − 1 8Tfmc_ker_ck + 1 FMC_NWE low time 6Tfmc_ker_ck − 1.5 6Tfmc_ker_ck + 0.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5Tfmc_ker_ck + 13 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4Tfmc_ker_ck+ 13 - tw(NE) tw(NWE) Parameter FMC_NE low time Unit ns 1. Guaranteed by characterization results. 2.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Table 67. Asynchronous multiplexed PSRAM/NOR read timings(1) Symbol Parameter Min Max 3Tfmc_ker_ck − 1 3Tfmc_ker_ck + 1 2Tfmc_ker_ck 2Tfmc_ker_ck + 0.5 Tfmc_ker_ck − 1 Tfmc_ker_ck + 1 FMC_NOE high to FMC_NE high hold time 0 - FMC_NEx low to FMC_A valid - 0.5 FMC_NEx low to FMC_NADV low 0 0.5 FMC_NADV low time Tfmc_ker_ck − 0.5 Tfmc_ker_ck+1 th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high Tfmc_ker_ck + 0.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB Figure 21. Asynchronous multiplexed PSRAM/NOR write waveforms tw(NE) FMC_ NEx FMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FMC_NWE th(A_NWE) tv(A_NE) FMC_ A[25:16] Address tv(BL_NE) th(BL_NWE) FMC_ NBL[1:0] NBL t v(A_NE) t v(Data_NADV) Address FMC_ AD[15:0] th(Data_NWE) Data th(AD_NADV) t v(NADV_NE) tw(NADV) FMC_NADV FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE) MS32756V1 Table 69.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Table 70. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1) Symbol Parameter FMC_NE low time tw(NE) tw(NWE) FMC_NWE low time tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid Min Max 9Tfmc_ker_ck – 1 9Tfmc_ker_ck 7Tfmc_ker_ck – 0.5 7Tfmc_ker_ck + 0.5 6Tfmc_ker_ck + 3 - 4Tfmc_ker_ck - Unit ns 1. Guaranteed by characterization results.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB Figure 22.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Table 71. Synchronous multiplexed NOR/PSRAM read timings(1) Symbol tw(CLK) Parameter FMC_CLK period td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB Figure 23.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Table 72. Synchronous multiplexed PSRAM write timings(1) Symbol tw(CLK) Parameter FMC_CLK period Min Max 2Tfmc_ker_ck − 1 - - 1 Tfmc_ker_ck + 0.5 - td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB Figure 24.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Figure 25. Synchronous non-multiplexed PSRAM write timings tw(CLK) tw(CLK) FMC_CLK td(CLKL-NExL) td(CLKH-NExH) Data latency = 0 FMC_NEx td(CLKL-NADVL) td(CLKL-NADVH) FMC_NADV td(CLKH-AIV) td(CLKL-AV) FMC_A[25:0] td(CLKL-NWEL) td(CLKH-NWEH) FMC_NWE td(CLKL-Data) td(CLKL-Data) D1 FMC_D[15:0] D2 FMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) td(CLKH-NBLH) th(CLKH-NWAITV) FMC_NBL MS32760V1 Table 74.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB NAND controller waveforms and timings Figure 26 through Figure 29 represent synchronous waveforms, and Table 75 and Table 76 provide the corresponding timings. The results shown in this table are obtained with the following FMC configuration: • COM.FMC_SetupTime = 0x01 • COM.FMC_WaitSetupTime = 0x03 • COM.FMC_HoldSetupTime = 0x02 • COM.FMC_HiZSetupTime = 0x01 • ATT.FMC_SetupTime = 0x01 • ATT.FMC_WaitSetupTime = 0x03 • ATT.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Figure 27. NAND controller waveforms for write access FMC_NCEx ALE (FMC_A17) CLE (FMC_A16) th(NWE-ALE) td(ALE-NWE) FMC_NWE FMC_NOE (NRE) th(NWE-D) tv(NWE-D) FMC_D[15:0] MS32768V1 Figure 28. NAND controller waveforms for common memory read access FMC_NCEx ALE (FMC_A17) CLE (FMC_A16) th(NOE-ALE) td(ALE-NOE) FMC_NWE tw(NOE) FMC_NOE tsu(D-NOE) th(NOE-D) FMC_D[15:0] MS32769V1 DS12556 Rev 2 143/201 189 Downloaded from Arrow.com.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB Figure 29. NAND controller waveforms for common memory write access FMC_NCEx ALE (FMC_A17) CLE (FMC_A16) td(ALE-NOE) tw(NWE) th(NOE-ALE) FMC_NWE FMC_N OE td(D-NWE) tv(NWE-D) th(NWE-D) FMC_D[15:0] MS32770V1 Table 75. Switching characteristics for NAND Flash read cycles(1) Symbol tw(N0E) Parameter FMC_NOE low width Min Max 4Tfmc_ker_ck − 0.5 4Tfmc_ker_ck + 0.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics SDRAM waveforms and timings In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period, with the following FMC_SDCLK maximum values: • For 1.8 V
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB Table 78. LPSDR SDRAM read timings(1) Symbol Parameter Min Max tW(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck − 1 2Tfmc_ker_ck + 0.5 tsu(SDCLKH_Data) Data input setup time 2 - th(SDCLKH_Data) Data input hold time 1.5 - td(SDCLKL_Add) Address valid time - 2.5 td(SDCLKL_SDNE) Chip select valid time - 2.5 th(SDCLKL_SDNE) Chip select hold time 0 - td(SDCLKL_SDNRAS SDNRAS valid time - 0.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Table 79. SDRAM write timings(1) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck − 1 2Tfmc_ker_ck + 0.5 td(SDCLKL _Data) Data output valid time - 3 th(SDCLKL _Data) Data output hold time 0 - td(SDCLKL_Add) Address valid time - 1.5 td(SDCLKL_SDNWE) SDNWE valid time - 1.5 th(SDCLKL_SDNWE) SDNWE hold time 0.5 - td(SDCLKL_ SDNE) Chip select valid time - 1.
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Electrical characteristics 6.3.18 STM32H750VB STM32H750IB STM32H750XB Quad-SPI interface characteristics Unless otherwise specified, the parameters given in Table 81 and Table 82 for Quad-SPI are derived from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage conditions summarized in Table 22: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Measurement points are done at CMOS levels: 0.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Table 82. Quad SPI characteristics in DDR mode(1) Symbol Fck1/t(CK) tw(CKH) Parameter Quad-SPI clock frequency Conditions Min Typ Max 2.7 V
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Electrical characteristics 6.3.19 STM32H750VB STM32H750IB STM32H750XB Delay block (DLYB) characteristics Unless otherwise specified, the parameters given in Table 84 for the delay block are derived from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage summarized in Table 22: General operating conditions. Table 83.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Table 84. ADC characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit fADC = 36 MHz - - 3.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB Table 85.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.15 does not affect the ADC accuracy. Figure 34.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB Figure 35. Typical connection diagram using the ADC STM32 VDD RAIN(1) AINx VAIN Cparasitic Sample and hold ADC converter VT 0.6 V RADC(1) VT 0.6 V IL±1 μA 12-bit converter C ADC(1) ai17534b 1. Refer to Table 84 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 5 pF).
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in Figure 36 or Figure 37, depending on whether VREF+ is connected to VDDA or not. The 100 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 36. Power supply and reference decoupling (VREF+ not connected to VDDA) STM32 VREF+(1) 1 μF // 100 nF VDDA 1 μF // 100 nF VSSA/VREF+(1) MSv50648V1 1.
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Electrical characteristics 6.3.21 STM32H750VB STM32H750IB STM32H750XB DAC electrical characteristics Table 86. DAC characteristics(1) Symbol Parameter Conditions Min Typ Max VDDA Analog supply voltage - 1.8 3.3 3.6 VREF+ Positive reference voltage - 1.80 - VDDA VREF- Negative reference voltage - - VSSA - connected to VSSA 5 - - connected to VDDA 25 - - 10.3 13 16 VDD = 2.7 V - - 1.6 VDD = 2.0 V - - 2.6 VDD = 2.7 V - - 17.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Table 86.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB Table 87. DAC accuracy(1) (continued) Symbol Parameter OffsetCal Offset error at code 0x800 after factory calibration Gain Gain Conditions error(5) DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 ㏀ VREF+ = 3.6 V Min Typ Max - - ±5 Unit LSB VREF+ = 1.
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STM32H750VB STM32H750IB STM32H750XB 6.3.22 Electrical characteristics Voltage reference buffer characteristics Table 88. VREFBUF characteristics(1) Symbol Parameter Conditions Normal mode VDDA Analog supply voltage Degraded mode Normal mode VREFBUF _OUT Voltage Reference Buffer Output Degraded mode Min Typ Max VSCALE = 000 2.8 3.3 3.6 VSCALE = 001 2.4 - 3.6 VSCALE = 010 2.1 - 3.6 VSCALE = 011 1.8 - 3.6 VSCALE = 000 1.62 - 2.80 VSCALE = 001 1.62 - 2.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB Table 88. VREFBUF characteristics(1) (continued) Symbol tSTART IINRUSH IDDA(VRE FBUF) Parameter Conditions Start-up time Typ Max CL=0.5 µF - - 300 - CL=1 µF - - 500 - CL=1.5 µF - - 650 - - 8 - Control of maximum DC current drive on VREFBUF_OUT during startup phase(3) - VREFBUF consumption from VDDA Min Unit µs mA ILOAD = 0 µA - - 15 25 ILOAD = 500 µA - - 16 30 ILOAD = 4 mA - - 32 50 µA 1.
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STM32H750VB STM32H750IB STM32H750XB 6.3.24 Electrical characteristics VBAT monitoring characteristics Table 91. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for VBAT - 26 - KΩ Q Ratio on VBAT measurement - 4 - - –10 - +10 % 9 - - µs Unit (1) Error on Q Er tS_vbat(1) ADC sampling time when reading VBAT input 1. Guaranteed by design. Table 92. VBAT charging characteristics Symbol RBC 6.3.
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Electrical characteristics 6.3.26 STM32H750VB STM32H750IB STM32H750XB Comparator characteristics Table 94. COMP characteristics(1) Symbol Conditions Min Typ Max Analog supply voltage - 1.62 3.3 3.6 Comparator input voltage range - 0 - VDDA VBG(2) Scaler input voltage - Refer to VREFINT VSC Scaler offset voltage - - ±5 ±10 BRG_EN=0 (bridge disable) - 0.2 0.3 BRG_EN=1 (bridge enable) - 0.
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STM32H750VB STM32H750IB STM32H750XB 6.3.27 Electrical characteristics Operational amplifiers characteristics Table 95. OPAMP characteristics(1) Symbol Parameter Conditions Min Typ Max Unit VDDA Analog supply voltage Range - 2 3.3 3.6 CMIR Common Mode Input Range - 0 - VDDA 25°C, no load on output - - ±1.5 All voltages and temperature, no load - - ±2.5 - - ±3.0 - Offset trim step at low TRIMOFFSETP common input voltage TRIMLPOFFSETP (0.1*V DDA) - - 1.1 1.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB Table 95. OPAMP characteristics(1) (continued) Symbol VOHSAT VOLSAT tWAKEUP Parameter Conditions Min Typ Max High saturation voltage Iload=max or RLOAD=min(2), Input at VDDA VDDA −100 mV - - Low saturation voltage Iload=max or RLOAD=min(2), Input at 0 V - - 100 Normal mode CLOAD ≤ 50pf, RLOAD ≥ 4 kΩ(2), follower configuration - 0.8 3.2 High speed CLOAD ≤ 50pf, RLOAD ≥ 4 kΩ(2), follower configuration - 0.9 2.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Table 95. OPAMP characteristics(1) (continued) Symbol en IDDA(OPAMP) Parameter Voltage noise density OPAMP consumption from VDDA Conditions at 1 KHz at 10 KHz Normal mode Highspeed mode output loaded with 4 kΩ no Load, quiescent mode, follower Min Typ Max - 140 - - 55 - - 570 1000 Unit nV/√ Hz µA - 610 1200 1. Guaranteed by design, unless otherwise specified. 2.
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Electrical characteristics 6.3.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Table 96. DFSDM measured timing 1.62-3.6 V(1) (continued) Symbol Parameter Conditions Min Typ Max twh(CKIN) twl(CKIN) Input clock high and low time SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.62 < VDD < 3.6 V TCKIN/2 - 0.5 TCKIN/2 - tsu Data input setup time SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.62 < VDD < 3.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB DFSDM_CKINy DFSDM_DATINy DFSDM_CKOUT (SPICKSEL=0) tsu th twl twh tr tf tr tf SITP = 00 tsu th SITP = 01 SPICKSEL=3 SPICKSEL=2 SPICKSEL=1 tsu DFSDM_DATINy SPI timing : SPICKSEL = 1, 2, 3 SPI timing : SPICKSEL = 0 Figure 39.
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STM32H750VB STM32H750IB STM32H750XB 6.3.
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Electrical characteristics 6.3.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Figure 41. LCD-TFT horizontal timing diagram tCLK LCD_CLK LCD_VSYNC tv(HSYNC) tv(HSYNC) LCD_HSYNC th(DE) tv(DE) LCD_DE tv(DATA) LCD_R[0:7] LCD_G[0:7] LCD_B[0:7] Pixel Pixel 1 2 Pixel N th(DATA) HSYNC Horizontal width back porch Active width Horizontal back porch One line MS32749V1 Figure 42.
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Electrical characteristics 6.3.31 STM32H750VB STM32H750IB STM32H750XB Timer characteristics The parameters given in Table 99 are guaranteed by design. Refer to Section 6.3.15: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 99.
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STM32H750VB STM32H750IB STM32H750XB 6.3.32 Electrical characteristics Communications interfaces I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev. 03 for: • Standard-mode (Sm): with a bit rate up to 100 kbit/s • Fast-mode (Fm): with a bit rate up to 400 kbit/s. • Fast-mode Plus (Fm+): with a bit rate up to 1Mbit/s.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB SPI interface characteristics Unless otherwise specified, the parameters given in Table 102 for the SPI interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 22: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Table 102. SPI dynamic characteristics(1) (continued) Symbol tsu(MI) tsu(SI) Parameter Data input setup time th(MI) Data input hold time th(SI) Conditions Min Typ Max Master mode 1 - - Slave mode 2 - - Master mode 2 - - Slave mode 1 - - ta(SO) Data output access time Slave mode 9 13 27 tdis(SO) Data output disable time Slave mode 0 1 5 Slave mode, 2.7 V≤VDD≤3.6 V - 11.5 16 Slave mode 1.62 V≤VDD≤3.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB Figure 44. SPI timing diagram - slave mode and CPHA = 1(1) NSS input tc(SCK) tsu(NSS) tw(SCKH) ta(SO) tw(SCKL) tf(SCK) th(NSS) SCK input CPHA=1 CPOL=0 CPHA=1 CPOL=1 tv(SO) th(SO) First bit OUT MISO output tsu(SI) tr(SCK) Next bits OUT tdis(SO) Last bit OUT th(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41659V1 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. Figure 45.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics I2S interface characteristics Unless otherwise specified, the parameters given in Table 103 for the I2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 22: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB Figure 46. I2S slave timing diagram (Philips protocol)(1) 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 47. I2S master timing diagram (Philips protocol)(1) 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. 178/201 Downloaded from Arrow.com.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics SAI characteristics Unless otherwise specified, the parameters given in Table 104 for SAI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 22: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C=30 pF • Measurement points are performed at CMOS levels: 0.5VDD Refer to Section 6.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB Figure 48. SAI master timing waveforms 1/fSCK SAI_SCK_X th(FS) SAI_FS_X (output) tv(FS) th(SD_MT) tv(SD_MT) SAI_SD_X (transmit) Slot n tsu(SD_MR) Slot n+2 th(SD_MR) SAI_SD_X (receive) Slot n MS32771V1 Figure 49.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Figure 50.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB Table 106. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V(1)(2) Symbol Parameter Conditions Min Typ Max 2 - - 1.5 - - - 1 2 0 - - Unit CMD, D inputs (referenced to CK) in SD default mode tISUD Input setup time SD tIHD Input hold time SD fPP =25 MHz ns CMD, D outputs (referenced to CK) in SD default mode tOVD Output valid default time SD tOHD Output hold default time SD fPP =25 MHz ns 1.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Figure 51. SDIO high-speed mode Figure 52. SD default mode CK tOVD tOHD D, CMD (output) ai14888 Figure 53. DDR mode tr(CK) t(CK) tw(CKH) tw(CKL) tf(CK) Clock tvf(OUT) Data output thr(OUT) D0 tvr(OUT) D1 D2 thf(OUT) D3 tsf(IN) thf(IN) Data input D0 D1 D4 D5 tsr(IN) thr(IN) D2 D3 D4 D5 MSv36879V1 CAN (controller area network) interface Refer to Section 6.3.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB USB OTG_FS characteristics The USB interface is fully compliant with the USB specification version 2.0 and is USB-IF certified (for Full-speed device operation). Table 108. USB OTG_FS electrical characteristics Symbol Parameter Condition Min Typ Max Unit USB transceiver operating voltage - 3.0(1) - 3.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Figure 54.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB Figure 55. Ethernet SMI timing diagram tMDC ETH_MDC td(MDIO) ETH_MDIO(O) tsu(MDIO) th(MDIO) ETH_MDIO(I) MS31384V1 Table 111 gives the list of Ethernet MAC signals for the RMII and Figure 56 shows the corresponding timing diagram. Table 111.
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Table 112. Dynamics characteristics: Ethernet MAC signals for MII(1) Symbol Parameter Min Typ Max tsu(RXD) Receive data setup time 2 - - tih(RXD) Receive data hold time 3 - - tsu(DV) Data valid setup time 1.5 - - tih(DV) Data valid hold time 1 - - tsu(ER) Error setup time 1.5 - - tih(ER) Error hold time 0.5 - - td(TXEN) Transmit enable valid delay time 4.5 6.
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Electrical characteristics STM32H750VB STM32H750IB STM32H750XB Table 113. Dynamics characteristics: JTAG characteristics(1) Symbol Parameter Fpp 1/tc(TCK) TCK clock frequency Conditions Min Typ Max 2.7 V
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STM32H750VB STM32H750IB STM32H750XB Electrical characteristics Figure 58. JTAG timing diagram tc(TCK) TCK tsu(TMS/TDI) th(TMS/TDI) tw(TCKL) tw(TCKH) TDI/TMS tov(TDO) toh(TDO) TDO MSv40458V1 Figure 59. SWD timing diagram tc(SWCLK) SWCLK tsu(SWDIO) th(SWDIO) twSWCLKL) tw(SWCLKH) SWDIO (receive) tov(SWDIO) toh(SWDIO) SWDIO (transmit) MSv40459V1 DS12556 Rev 2 189/201 189 Downloaded from Arrow.com.
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Package information 7 STM32H750VB STM32H750IB STM32H750XB Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at www.st.com. ECOPACK® is an ST trademark. 7.1 LQFP100 package information Figure 60. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline 0.
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STM32H750VB STM32H750IB STM32H750XB Package information Table 115. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.
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Package information STM32H750VB STM32H750IB STM32H750XB Figure 61. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint 75 76 51 50 0.5 0.3 16.7 14.3 100 26 1.2 1 25 12.3 16.7 ai14906c 1. Dimensions are expressed in millimeters. 192/201 Downloaded from Arrow.com.
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STM32H750VB STM32H750IB STM32H750XB 7.2 Package information UFBGA176+25 package information Figure 62. UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package outline C Seating plane A4 ddd C A3 A2 A1 b e A A1 ball identifier E1 A1 ball index area A E Z A Z D1 D e B R 15 1 BOTTOM VIEW Øb (176 + 25 balls) TOP VIEW Ø eee M C A B Ø fff M C A0E7_ME_V8 1. Drawing is not to scale. Table 116. UFBGA176+25 - ball, 10 x 10 mm, 0.
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Package information STM32H750VB STM32H750IB STM32H750XB Table 116. UFBGA176+25 - ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 63. UFBGA176+25 - 201-ball, 10 x 10 mm, 0.
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STM32H750VB STM32H750IB STM32H750XB 7.3 Package information TFBGA240+25 package information ddd C Figure 64. TFBGA - 240+25 ball, 14x14 mm, 0.8 mm pitch, fine pitch ball grid array package outline A1 A C A2 SEATING PLANE A1 ball identifier D1 D e E1 E G A e S 1 17 F BOTTOM VIEW b (240 + 25 balls) TOP VIEW A07U_ME_V1 1. Dimensions are expressed in millimeters. DS12556 Rev 2 195/201 199 Downloaded from Arrow.com.
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Package information STM32H750VB STM32H750IB STM32H750XB Table 118. TFBG - 240 +25 ball, 14x14 mm, 0.8 mm pitch, fine pitch ball grid array mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.100 - - 0.0433 A1 0.150 - - 0.0059 - - A2 - 0.760 - - 0.0299 - b 0.350 0.400 0.450 0.0138 0.0157 0.0177 D 13.850 14.000 14.150 0.5453 0.5512 0.5571 D1 - 12.800 - - 0.5039 - E 13.850 14.000 14.150 0.5453 0.5512 0.5571 E1 - 12.
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STM32H750VB STM32H750IB STM32H750XB Package information Table 119. TFBGA - 240+25ball recommended PCB design rules (0.8 mm pitch) Dimension Recommended values Pitch 0.8 mm Dpad 0.225 mm Dsm 0.290 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.250 mm Stencil thickness 0.100 mm DS12556 Rev 2 197/201 199 Downloaded from Arrow.com.
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Package information 7.4 STM32H750VB STM32H750IB STM32H750XB Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max × ΘJA) Where: • TA max is the maximum ambient temperature in ° C, • ΘJA is the package junction-to-ambient thermal resistance, in ° C/W, • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), • PINT max is the product of IDD and VDD, expressed in Watts.
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STM32H750VB STM32H750IB STM32H750XB 8 Ordering information Ordering information Table 121. STM32H750xB ordering information scheme Example: STM32 H 750 V B T 6 TR Device family STM32 = Arm-based 32-bit microcontroller Product type H = High performance Device subfamily 750 = STM32H750 value line with cryptographic accelerator Pin count V = 100 pins I = 176 pins/balls X = 240 balls Flash memory size B = 128 Kbytes Package T = LQFP K = UFBGA pitch 0.
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Revision history 9 STM32H750VB STM32H750IB STM32H750XB Revision history Table 122. Document revision history Date Revision 21-May-2018 1 Initial release. 2 Changed datasheet status to “production data”. Added description of power-up and power-down phases in Section 3.5.1: Power supply scheme. Updated Table 44: HSI48 oscillator characteristics, Table 45: HSI oscillator characteristics and Table 46: CSI oscillator characteristics.
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STM32H750VB STM32H750IB STM32H750XB IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.