Datasheet

DocID030538 Rev 3 27/226
STM32H743xI Functional overview
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3.12 Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller which is able to manage 16
priority levels, and handle up to 150 maskable interrupt channels plus the 16 interrupt lines
of the Cortex
®
-M7 with FPU core.
• Closely co
upled NVIC gives low-latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Allows early processing of interrupts
• Processing of late arriving, higher-priority interrupts
• Support tail chaining
• Processor context automatically saved on interrupt entry, and restored on interrupt exit
with no instruction overhead
This hardware block provides fle
xible interrupt management features with minimum interrupt
latency.
3.13 Extended interrupt and event controller (EXTI)
The EXTI controller performs interrupt and event management. In addition, it can wake up
the processor, power domains and/or D3 domain from Stop mode.
The EXTI handles up to 89 independent event/inter
rupt lines split as 28 configurable events
and 61 direct events .
Configurable events have dedicated pending flags, active edg
e selection, and software
trigger capable.
Direct events provide interrupts or events
from peripherals having a status flag.
3.14 Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
programmable polynomial.
Among other applications, CRC-based techniques ar
e used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
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