Datasheet

Electrical characteristics STM32H743xI
158/226 DocID030538 Rev 3
Equation 1: R
AIN
max formula
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution).
f
TRIG
External trigger frequency
f
ADC
= 36 MHz - - 3.6 MHz
16-bit resolution - - 10 1/f
ADC
V
AIN
(2)
Conversion voltage range - 0 - V
REF+
V
V
CMIV
Common mode input
voltage
-
V
REF
/2
10%
V
REF
/2
V
REF
/2+
10%
R
AIN
External input impedance See Equation 1 for details - - 50 ㏀
C
ADC
Internal sample and hold
capacitor
--4-pF
t
ADCREG_
STUP
ADC LDO startup time - - 5 10 µs
t
STAB
ADC power-up time LDO already started 1
conversion
cycle
t
CAL
Offset and linearity
calibration time
- 16384
1/f
ADC
t
OFF_CAL
Offset calibration time - 1280
t
LATR
Trigger conversion latency
for regular and injected
channels without aborting
the conversion
CKMODE = 00 1.5 2 2.5
CKMODE = 01 - - 2
CKMODE = 10 2.25
CKMODE = 11 2.125
t
LATRINJ
Trigger conversion latency
for regular and injected
channels when a regular
conversion is aborted
CKMODE = 00 2.5 3 3.5
CKMODE = 01 - - 3
CKMODE = 10 - - 3.25
CKMODE = 11 - - 3.125
t
S
Sampling time - 1.5 - 640.5
t
CONV
Total conversion time
(including sampling time)
N-bit resolution
t
S
+ 0.5 + N/2
(9 to 648 cycles in 14-bit
mode)
1. Guaranteed by design.
2. Depending on the package, V
REF+
can be internally connected to V
DDA
and V
REF-
to V
SSA
.
Table 84. ADC characteristics
(1)
(continued)
Symbol Parameter Conditions Min Typ Max Unit
R
AIN
k0.5–()
f
ADC
C
ADC
2
N 2+
()ln××
---------------------------------------------------------------- R
ADC
–<
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