Datasheet

Functional overview STM32H743xI
28/226 DocID030538 Rev 3
3.15 Flexible memory controller (FMC)
The FMC controller main features are the following:
• Inter
face with static-memory mapped devices including:
– Static random access memory (SRAM)
– NOR Flash memory/OneNAND Flash memory
– PSRAM (4 memory banks)
– NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
• Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
• 8-,16-,32-bit data bus width
• Independent Chip Select control for each memory bank
• Independent configuration for each memory bank
• Write FIFO
• Read FIFO for SDRAM controller
• The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is the
FMC kernel clock divided by 2.
3.16 Quad-SPI memory interface (QUADSPI)
All devices embed a Quad-SPI memory interface, which is a specialized communication
interface targeting Single, Dual or Quad-SPI Flash memories. It supports both single and
double datarate operations.
It can operate in any of the following modes:
• Dir
ect mode through registers
• External Flash status register polling mode
• Memory mapped mode.
Up to 256 Mbytes of external Flash memory can be mapped, and 8-, 16- and 32-bit data
a
ccesses are supported as well as code execution.
The opcode and the frame format are fully programmable.
3.17 Analog-to-digital converters (ADCs)
The STM32H743xI devices embed three analog-to-digital converters, which resolution can
be configured to 16, 14, 12, 10 or 8 bits. Each ADC shares up to 20 external channels,
performing conversions in the single-shot or scan mode. In scan mode, automatic
conversion is performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
• Simulta
neous sample and hold
• Interleaved sample and hold
The ADC can be served by the DMA controller, thus allowing to automatically transfer ADC
co
nverted values to a destination location without any software action.
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