Datasheet
Functional overview STM32H743xI
22/226 DocID030538 Rev 3
The devices feature several low-power modes:
• CSleep (CPU clock stopped)
• CStop (CPU sub-system clock stopped)
• DStop (Domain bus matrix clock stopped)
• Stop (System clock stopped)
• DStandby (Domain powered down)
• Standby (System powered down)
CSleep and CStop low-power modes are entered by the MCU when executing the WFI
(W
ait for Interrupt) or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit of
the Cortex
®
-Mx core is set after returning from an interrupt service routine.
A domain can enter low-power mode (DStop or DStandby) when the processor, its
sub
system and the peripherals allocated in the domain enter low-power mode.
If part of the domain is not in low-power mode, the domain remains in the current mode.
Finally the system can enter Stop or Standby when all EXTI wakeup sources are cleared
an
d the power domains are in DStop or DStandby mode.
3.7 Reset and clock controller (RCC)
The clock and reset controller is located in D3 domain. The RCC manages the generation of
all the clocks, as well as the clock gating and the control of the system and peripheral
resets. It provides a high flexibility in the choice of clock sources and allows to apply clock
ratios to improve the power consumption. In addition, on some communication peripherals
that are capable to work with two different clock domains (either a bus interface clock or a
kernel peripheral clock), the system frequency can be changed without modifying the
baudrate.
Table 3. System vs domain low-power mode
System power mode
D1 domain power
mode
D2 domain power
mode
D3 domain power
mode
Run DRun/DStop/DStandby DRun/DStop/DStandby DRun
Stop DStop/DStandby DStop/DStandby DStop
Standby DStandby DStandby DStandby
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