Datasheet

Electrical characteristics STM32H743xI
148/226 DocID030538 Rev 3
Figure 29. Synchronous non-multiplexed PSRAM write timings
MS32760V1
FMC_CLK
FMC_NEx
FMC_A[25:0]
FMC_NWE
FMC_D[15:0]
D1 D2
FMC_NWAIT
(WAITCFG = 0b, WAITPOL + 0b)
t
w(CLK)
t
w(CLK)
Data latency = 0
t
d(CLKL-NExL)
t
d(CLKH-NExH)
t
d(CLKL-AV)
t
d(CLKH-AIV)
t
d(CLKH-NWEH)
t
d(CLKL-NWEL)
t
d(CLKL-Data)
t
su(NWAITV-CLKH)
t
h(CLKH-NWAITV)
FMC_NADV
t
d(CLKL-NADVL)
t
d(CLKL-NADVH)
t
d(CLKL-Data)
FMC_NBL
t
d(CLKH-NBLH)
Table 74. Synchronous non-multiplexed PSRAM write timings
(1)
Symbol Parameter Min Max Unit
t
(CLK)
FMC_CLK period 2T
fmc_ker_ck
− 1 -
ns
t
d(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x=0..2) - 2
t
(CLKH-NExH)
FMC_CLK high to FMC_NEx high (x= 0…2) T
fmc_ker_ck
+ 0.5 -
t
d(CLKL-NADVL)
FMC_CLK low to FMC_NADV low - 0.5
t
d(CLKL-NADVH)
FMC_CLK low to FMC_NADV high 0 -
t
d(CLKL-AV)
FMC_CLK low to FMC_Ax valid (x=16…25) - 2
t
d(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid (x=16…25) T
fmc_ker_ck
-
t
d(CLKL-NWEL)
FMC_CLK low to FMC_NWE low - 1.5
t
d(CLKH-NWEH)
FMC_CLK high to FMC_NWE high T
fmc_ker_ck
+ 1 -
t
d(CLKL-Data)
FMC_D[15:0] valid data after FMC_CLK low - 3.5
t
d(CLKL-NBLL)
FMC_CLK low to FMC_NBL low - 2
t
d(CLKH-NBLH)
FMC_CLK high to FMC_NBL high T
fmc_ker_ck
+ 1 -
t
su(NWAIT-CLKH)
FMC_NWAIT valid before FMC_CLK high 2 -
t
h(CLKH-NWAIT)
FMC_NWAIT valid after FMC_CLK high 2 -
1. Guaranteed by characterization results.
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