Datasheet

Electrical characteristics STM32H743xI
130/226 DocID030538 Rev 3
Output voltage levels
Unless otherwise specified, the parameters given in Table 59 are derived from tests
performed under ambient temperature and V
DD
supply voltage conditions summarized in
Table 23: General operating conditions. All I/Os are CMOS and TTL compliant.
Table 59. Output voltage characteristics
(1)
Symbol Parameter Conditions
(3)
Min Max Unit
V
OL
Output low level voltage
CMOS port
(2)
I
IO
=8 mA
2.7 V V
DD
3.6 V
0.4
V
V
OH
Output high level voltage
CMOS port
(2)
I
IO
=-8 mA
2.7 V V
DD
3.6 V
V
DD
0.4
V
OL
(3)
Output low level voltage
TTL port
(2)
I
IO
=8 mA
2.7 V V
DD
3.6 V
0.4
V
OH
(3)
Output high level voltage
TTL port
(2)
I
IO
=-8 mA
2.7 V V
DD
3.6 V
2.4
V
OL
(3)
Output low level voltage
I
IO
=20 mA
2.7 V V
DD
3.6 V
1.3
V
OH
(3)
Output high level voltage
I
IO
=-20 mA
2.7 V V
DD
3.6 V
V
DD
1.3
V
OL
(3)
Output low level voltage
I
IO
=4 mA
1.62 V V
DD
3.6 V
0.4
V
OH
(3)
Output high level voltage
I
IO
=-4 mA
1.62 VV
DD
<3.6 V
V
DD
-0.4
V
OLFM+
(3)
Output low level voltage for an FTf
IO pin in FM+ mode
I
IO
= 20 mA
2.3 V V
DD
3.6 V
-0.4
I
IO
= 10 mA
1.62 V V
DD
3.6 V
-0.4
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 20:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings IIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Guaranteed by design.
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