Datasheet

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This is information on a product in full production.

October 2017 DocID030538 Rev 3 1/226

STM32H743xI

32-bit Arm

Cortex

-M7 400MHz MCUs, up to 2MB Flash,

1MB RAM, 46 com. and analog interfaces

Datasheet - production data

Features

Core

• 32-bit Arm

Cortex

-M7 core with double-

precision FPU and L1 cache: 16 Kbytes of data

and 16 Kbytes of instruction cache allowing

one cache line to be filled in a single access

from the 256-bit embedded Flash memory;

frequency up to 400 MHz, MPU, 856 DMIPS/

2.14 DMIPS/MHz (Dhrystone 2.1), and DSP

instructions

Memories

• Up to 2 Mbytes of Flash memory with read-

while-write support

• 1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc.

64 Kbytes of ITCM RAM + 128 Kbytes of

DTCM RAM for time critical routines),

864 Kbytes of user SRAM, and 4 Kbytes of

SRAM in Backup domain

• Dual mode Quad-SPI memory interface

running up to 133 MHz

• Flexible external memory controller with up to

32-bit data bus: SRAM, PSRAM,

SDRAM/LPSDR SDRAM, NOR/NAND Flash

clocked up to 133 MHz in synchronous mode

• CRC calculation unit

Security

• ROP, PC-ROP, active tamper

General-purpose input/outputs

• Up to 168 I/O ports with interrupt capability

– Fast I/Os capable of up to 133 MHz

– Up to 164 5 V-tolerant I/Os

Reset and power management

• 3 separate power domains which can be

independently clock gated or switched off to

maximize power efficiency:

– D1: high-performance capabilities for high

bandwidth peripherals

– D2: communication peripherals and timers

– D3: reset/clock control/power management

• 1.62 to 3.6 V application supply and I/Os

• POR, PDR, PVD and BOR

• Dedicated USB power embedding a 3.3 V

internal regulator to supply the internal PHYs

• Embedded regulator (LDO) with configurable

scalable output to supply the digital circuitry

• Voltage scaling in Run and Stop mode (5

configurable ranges)

• Backup regulator (~0.9 V)

• Voltage reference for analog peripheral/V

REF+

• Low-power modes: Sleep, Stop, Standby and

BAT

supporting battery charging

Low-power consumption

• Total current consumption down to 4

µA

Clock management

• Internal oscillators: 64 MHz HSI, 48 MHz

HSI48, 4 MHz CSI, 40 kHz LSI

• External oscillators: 4-48 MHz HSE,

32.768 kHz LSE

• 3× PLLs (1 for the system clock, 2 for kernel

clocks) with fractional mode

FBGA

LQFP208

(28x28 mm)

LQFP176

(24x24 mm)

LQFP144

(20x20 mm)

LQFP100

(14x14 mm)

UFBGA176+25 (10x10 mm)

UFBGA169 (7x7 mm)

(1)

FBGA

TFBGA240+25 (14x14 mm)

TFBGA100 (8x8 mm)

(1)

1. Package under development.

www.st.com

Downloaded from Arrow.com.

Summary of content (226 pages)

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STM32H743xI 32-bit Arm® Cortex®-M7 400MHz MCUs, up to 2MB Flash, 1MB RAM, 46 com. and analog interfaces Datasheet - production data Features FBGA Core • 32-bit Arm® Cortex®-M7 core with doubleprecision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction cache allowing one cache line to be filled in a single access from the 256-bit embedded Flash memory; frequency up to 400 MHz, MPU, 856 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.
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STM32H743xI Interconnect matrix • 1× temperature sensor • 3 bus matrices (1 AXI and 2 AHB) • 2× 12-bit D/A converters (1 MHz) • Bridges (5× AHB2-APB, 2× AXI2-AHB) • 2× ultra-low-power comparators 4 DMA controllers to unload the CPU • 1× high-speed general-purpose master direct memory access controller (MDMA) with linked list support • 2× dual-port DMAs with FIFO and request router capabilities • 2× operational amplifiers (8 MHz bandwidth) • 1× digital filters for sigma delta modulator (DFSDM) with
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STM32H743xI Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 Arm® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 Memory protection unit (MPU) . . . .
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Contents 4 4/226 Downloaded from Arrow.com. STM32H743xI 3.21 Ultra-low-power comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.22 Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.23 Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 31 3.24 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.25 LCD-TFT controller . . . . . . . . . . .
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STM32H743xI Contents 5 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . .
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Contents 7 STM32H743xI 6.3.25 Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 6.3.26 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 6.3.27 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 170 6.3.28 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics . . . 173 6.3.29 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . .
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STM32H743xI List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . . . . . . . . .
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List of tables Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93.
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STM32H743xI Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. List of tables DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of figures STM32H743xI List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43.
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STM32H743xI Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. List of figures SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . .
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Introduction 1 STM32H743xI Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32H743xI microcontrollers. This document should be read in conjunction with the STM32H743xI reference manual (RM0433). The reference manual is available from the STMicroelectronics website www.st.com. For information on the Arm® Cortex®-M7 core, please refer to the Cortex®-M7 Technical Reference Manual, available from the www.arm.com website.
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STM32H743xI 2 Description Description STM32H743xI devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC core operating at up to 400 MHz. The Cortex® -M7 core features a floating point unit (FPU) which supports Arm® double-precision (IEEE 754 compliant) and single-precision dataprocessing instructions and data types. STM32H743xI devices support a full set of DSP instructions and a memory protection unit (MPU) to enhance application security.
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Description STM32H743xI STM32H743xI devices operate in the –40 to +85 °C temperature range from a 1.62 to 3.6 V power supply. The supply voltage can drop down to 1.62 V by using an external power supervisor (see Section 3.5.2: Power supply supervisor) and connecting the PDR_ON pin to VSS. Otherwise the supply voltage must stay above 1.71 V with the embedded power voltage detector enabled.
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STM32H743xI Description Table 2.
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Description STM32H743xI Table 2. STM32H743xI features and peripheral counts (continued) Peripherals STM32H 743VI STM32H 743AI STM32H 743II STM32H 743BI STM32H 743XI Ambient temperatures: –40 up to +85 °C(4) Operating temperatures Package STM32H 743ZI Junction temperature: –40 to + 125 °C LQFP100 TFBGA100(5) LQFP144 UFBGA 169(5) LQFP176 UFBGA 176+25 LQFP208 TFBGA 240+25 1.
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STM32H743xI Description Figure 1.
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Functional overview STM32H743xI 3 Functional overview 3.1 Arm® Cortex®-M7 with FPU The Arm® Cortex®-M7 with double-precision FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and optimized power consumption, while delivering outstanding computational performance and low interrupt latency.
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STM32H743xI Functional overview 3.3 Memories 3.3.1 Embedded Flash memory The STM32H743xI devices embed up to 2 Mbytes of Flash memory that can be used for storing programs and data. The Flash memory is organized as 266-bit Flash words memory that can be used for storing both code and data constants. Each word consists of: • One Flash word (8 words, 32 bytes or 256 bits) • 10 ECC bits. The Flash memory is divided into two independent banks. Each bank is organized as follows: 3.3.
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Functional overview STM32H743xI SRAM data are protected by ECC: • 7 ECC bits are added per 32-bit word. • 8 ECC bits are added per 64-bit word for AXI-SRAM and ITCM-RAM. The ECC mechanism is based on the SECDED algorithm. It supports single- and doubleerror correction. 3.
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STM32H743xI 3.5.2 Functional overview Power supply supervisor The devices have an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry: • Power-on reset (POR) The POR supervisor monitors VDD power supply and compares it to a fixed threshold. The devices remain in reset mode when VDD is below this threshold, • Power-down reset (PDR) The PDR supervisor monitors VDD power supply. A reset is generated when VDD drops below a fixed threshold.
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Functional overview STM32H743xI The devices feature several low-power modes: • CSleep (CPU clock stopped) • CStop (CPU sub-system clock stopped) • DStop (Domain bus matrix clock stopped) • Stop (System clock stopped) • DStandby (Domain powered down) • Standby (System powered down) CSleep and CStop low-power modes are entered by the MCU when executing the WFI (Wait for Interrupt) or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit of the Cortex®-Mx core is set after returning from
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STM32H743xI 3.7.1 Functional overview Clock management The devices embed four internal oscillators, two oscillators with external crystal or resonator, two internal oscillators with fast startup time and three PLLs. The RCC receives the following clock source inputs: • • Internal oscillators: – 64 MHz HSI clock (1% accuracy) – 48 MHz RC oscillator – 4 MHz CSI clock – 32 kHz LSI clock External oscillators: – 4-48 MHz HSE clock – 32.
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Functional overview 3.9 STM32H743xI Bus-interconnect matrix The devices feature an AXI bus matrix, two AHB bus matrices and bus bridges that allow interconnecting bus masters with bus slaves (see Figure 2). 24/226 Downloaded from Arrow.com.
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DocID030538 Rev 3 MDMA DMA2D Slave interface Bus multiplexer LTDC Master interface TCM AHB AXI APB 64-bit AXI bus matrix D1 domain SDMMC1 DTCM 128 Kbyte ITCM 64 Kbyte 64-bit bus 32-bit bus AXIM I$ D$ 16KB 16KB D2-to-D1 AHB Legend CPU AHBP Cortex-M7 D1-to-D3 AHB FMC QSPI AXI SRAM 512 Kbyte Flash B 1 Mbyte Flash A 1 Mbyte BDMA Backup SRAM 4 Kbyte SRAM4 64 Kbyte AHB4 APB4 32-bit AHB bus matrix D3 domain D2-to-D3 AHB APB2 APB1 AHB2 AHB1 SRAM3 32 Kbyte SRAM2 128 Kbyte AHB3
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Functional overview 3.10 STM32H743xI DMA controllers The devices feature four DMA instances to unload CPU activity: • A master direct memory access (MDMA) The MDMA is a high-speed DMA controller, which is in charge of all types of memory transfers (peripheral to memory, memory to memory, memory to peripheral), without any CPU action. It features a master AXI interface and a dedicated AHB interface to access Cortex®-M7 TCM memories. The MDMA is located in D1 domain.
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STM32H743xI 3.12 Functional overview Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller which is able to manage 16 priority levels, and handle up to 150 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-M7 with FPU core.
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Functional overview 3.15 STM32H743xI Flexible memory controller (FMC) The FMC controller main features are the following: • Interface with static-memory mapped devices including: – 3.
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STM32H743xI Functional overview In addition, an analog watchdog feature can accurately monitor the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1, TIM2, TIM3, TIM4, TIM6, TIM8, TIM15, HRTIM1 and LPTIM1 timer. 3.
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Functional overview 3.20 STM32H743xI Digital-to-analog converters (DAC) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs.
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STM32H743xI Functional overview The devices embeds two operational amplifiers (OPAMP1 and OPAMP2) with two inputs and one output each. These three I/Os can be connected to the external pins, thus enabling any type of external interconnections. The operational amplifiers can be configured internally as a follower, as an amplifier with a non-inverting gain ranging from 2 to 16 or with inverting gain ranging from -1 to -15. 3.
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Functional overview • STM32H743xI short circuit detector to detect saturated analog input values (bottom and top range): – up to 8-bit counter to detect 1..
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STM32H743xI 3.25 Functional overview LCD-TFT controller The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue) and delivers all signals to interface directly to a broad range of LCD and TFT panels up to XGA (1024x768) resolution with the following features: 3.
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Functional overview STM32H743xI All timer counters can be frozen in debug mode. Table 5 compares the features of the advanced-control, general-purpose and basic timers. Table 5. Timer feature comparison Timer type Timer Highresolution HRTIM1 timer Advanced -control TIM1, TIM8 TIM2, TIM5 TIM3, TIM4 TIM12 Counter Counter Prescaler resolution type factor TIM15 TIM16, TIM17 34/226 Downloaded from Arrow.com.
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STM32H743xI Functional overview Table 5. Timer feature comparison (continued) Timer type DMA Capture/ request compare generation channels Complementary output Max Max interface timer clock clock (MHz) (MHz)(1) Timer Counter Counter Prescaler resolution type factor Basic TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No 100 200 Lowpower timer LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5 16-bit Up 1, 2, 4, 8, 16, 32, 64, 128 No 0 No 100 200 1.
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Functional overview 3.28.2 STM32H743xI Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers.
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STM32H743xI 3.28.4 Functional overview Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base. TIM6 and TIM7 support independent DMA request generation. 3.28.5 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) The low-power timers have an independent clock and is running also in Stop mode if it is clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode.
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Functional overview 3.29 STM32H743xI Real-time clock (RTC), backup SRAM and backup registers The RTC is an independent BCD timer/counter. It supports the following features: • Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format. • Automatic correction for 28, 29 (leap year), 30, and 31 days of the month. • Two programmable alarms. • On-the-fly correction from 1 to 32767 RTC clock pulses.
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STM32H743xI 3.30 Functional overview Inter-integrated circuit interface (I2C) STM32H743xI devices embed four I2C interfaces. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: • • 3.31 I2C-bus specification and user manual rev.
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Functional overview STM32H743xI All USART have a clock domain independent from the CPU clock, allowing the USARTx to wake up the MCU from Stop mode.The wakeup from Stop mode are programmable and can be done on: • Start bit detection • Any received data frame • A specific programmed data frame • Specific TXFIFO/RXFIFO status when FIFO mode is enabled. All USART interfaces can be served by the DMA controller. Table 6.
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STM32H743xI Functional overview The LPUART has a clock domain independent from the CPU clock, and can wakeup the system from Stop mode. The wakeup from Stop mode are programmable and can be done on: • Start bit detection • Any received data frame • A specific programmed data frame • Specific TXFIFO/RXFIFO status when FIFO mode is enabled. Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud.
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Functional overview 3.35 STM32H743xI SPDIFRX Receiver Interface (SPDIFRX) The SPDIFRX peripheral is designed to receive an S/PDIF flow compliant with IEC-60958 and IEC-61937. These standards support simple stereo streams up to high sample rate, and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up to 5.1). The main SPDIFRX features are the following: • Up to 4 inputs available • Automatic symbol rate detection • Maximum symbol rate: 12.
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STM32H743xI 3.37 Functional overview Management Data Input/Output (MDIO) slaves The devices embed an MDIO slave interface it includes the following features: • – 32 x 16-bit firmware read/write, MDIO read-only output data registers – 32 x 16-bit firmware read-only, MDIO write-only input data registers • Configurable slave (port) address • Independently maskable interrupts/events: • 3.
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Functional overview 3.40 STM32H743xI Universal serial bus on-the-go high-speed (OTG_HS) The devices embed two USB OTG high-speed (up to 480 Mbit/s) device/host/OTG peripheral. OTG-HS1 supports both full-speed and high-speed operations, while OTG-HS2 supports only full-speed operations. They both integrate the transceivers for full-speed operation (12 Mbit/s). OTG-HS1 features a UTMI low-pin interface (ULPI) for high-speed operation (480 Mbit/s).
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STM32H743xI Functional overview The devices include the following features: 3.
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Memory mapping 4 STM32H743xI Memory mapping Refer to the product line reference manual for details on the memory mapping as well as the boundary addresses for all peripherals. 46/226 Downloaded from Arrow.com.
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STM32H743xI 5 Pin descriptions Pin descriptions PA14 PA15 PC10 PC11 PC12 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PB3 PB4 PB5 PB6 PB7 BOOT0 PB8 PB9 PE0 PE1 VSS VDD Figure 3.
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Pin descriptions STM32H743xI Figure 4.
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STM32H743xI Pin descriptions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 144-pins 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 VDD VSS VCAP2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDD33USB VSS PG8 PG7 PG6 PG5 PG4 PG3 PG2 PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8
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Pin descriptions STM32H743xI Figure 6.
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STM32H743xI Pin descriptions PE2 PE3 PE4 PE5 PE6 VBAT PI8 PC13 PC14-OSC32_IN PC15-OSC32_OUT PI9 PI10 PI11 VSS VDD PF0 PF1 PF2 PF3 PF4 PF5 VSS VDD PF6 PF7 PF8 PF9 PF10 PH0-OSC_IN PH1-OSC_OUT NRST PC0 PC1 PC2_C PC3_C VDD VSSA VREF+ VDDA PA0-WKUP PA1 PA2 PH2 PH3 134 133 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 PINOUT UNDER DEVELOPMENT 169 170 171 172 173 174 175 176 PI7
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Pin descriptions STM32H743xI Figure 8.
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STM32H743xI Pin descriptions 208-pins 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 3
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Pin descriptions STM32H743xI Figure 10.
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STM32H743xI Pin descriptions Table 7. Legend/abbreviations used in the pinout table Name Pin name Pin type Abbreviation Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin I/O Input / output pin ANA Analog-only Input FT 5 V tolerant I/O TT 3.
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Pin descriptions STM32H743xI Table 8.
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STM32H743xI Pin descriptions Table 8.
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Pin descriptions STM32H743xI Table 8.
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STM32H743xI Pin descriptions Table 8.
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Pin descriptions STM32H743xI Table 8.
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STM32H743xI Pin descriptions Table 8.
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Pin descriptions STM32H743xI Table 8.
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STM32H743xI Pin descriptions Table 8.
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Pin descriptions STM32H743xI Table 8.
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STM32H743xI Pin descriptions Table 8.
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Pin descriptions STM32H743xI Table 8.
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STM32H743xI Pin descriptions Table 8.
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Pin descriptions STM32H743xI Table 8.
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STM32H743xI Pin descriptions Table 8.
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Pin descriptions STM32H743xI Table 8.
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STM32H743xI Pin descriptions Table 8.
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Pin descriptions STM32H743xI Table 8.
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STM32H743xI Pin descriptions Table 8.
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Pin descriptions STM32H743xI Table 8.
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STM32H743xI Pin descriptions Table 8.
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Pin descriptions STM32H743xI Table 8.
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STM32H743xI Pin descriptions Table 8.
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Pin descriptions STM32H743xI Table 8.
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STM32H743xI Pin descriptions 3. This ball should be connected to VSS. 4. Pxy_C and Pxy pins/balls are two separate pads (analog switch open). The analog switch is configured through a SYSCFG register. Refer to the product reference manual for a detailed description of the switch configuration bits. 5. There is a direct path between Pxy_C and Pxy pins/balls, through an analog switch. Pxy alternate functions are available on Pxy_C when the analog switch is closed.
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DocID030538 Rev 3 NJTRST - - - - PB5 PB6 PB7 PB8 TIM2_CH2 JTDO/TRA CESWO PB3 PB4 - - PB2 TIM4_CH1 TIM4_CH2 TIM16_CH1 N TIM17_CH1 N TIM4_CH3 TIM3_CH2 TIM17_ BKIN TIM16_CH1 TIM3_CH1 HRTIM_ FLT4 SAI1_D1 TIM3_CH4 TIM3_CH3 SAI1/TIM3/ 4/5/12/ HRTIM1 TIM16_ BKIN TIM1_CH3N - PB1 TIM1_CH2N - PB0 SYS TIM1/2/16/1 7/LPTIM1/ HRTIM1 AF1 AF0 Port HRTIM_ FLT1 TIM2_CH1/ TIM2_ETR JTDI PA15 AF2 - - JTCKSWCLK PA14 SAI1/TIM3/ 4/5/12/ HRTIM1 AF2 SYS AF1 TIM1/2/16/1 7/LPTIM1
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Electrical characteristics 6 STM32H743xI Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of junction temperature, supply voltage and frequencies by tests in production on 100% of the devices with an junction temperature at TJ = 25 °C and TJ = TJmax (given by the selected temperature range).
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STM32H743xI 6.1.6 Electrical characteristics Power supply scheme VDD33USB 100 nF 100 nF Figure 13. Power supply scheme VDD33USB USB regulator VDDLDO VCAP Core domain (VCORE) Level shifter VSS IOs N(1) x 100 nF + 1 x 4.
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Electrical characteristics 6.1.7 STM32H743xI Current consumption measurement Figure 14. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 20: Voltage characteristics, Table 21: Current characteristics, and Table 22: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied.
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STM32H743xI Electrical characteristics Table 21.
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Electrical characteristics STM32H743xI 6.3 Operating conditions 6.3.1 General operating conditions Table 23. General operating conditions(1) Symbol Parameter Operating conditions Min Max (2) 3.6 VDD Standard operating voltage - VDDLDO Supply voltage for the internal regulator VDDLDO ≤ VDD 1.62(2) 3.6 USB used 3.0 3.6 USB not used 0 3.6 ADC or COMP used 1.62 DAC used 1.8 OPAMP used 2.0 VREFBUF used 1.8 ADC, DAC, OPAMP, COMP, VREFBUF not used 0 TT_xx I/O −0.3 VDD+0.
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STM32H743xI Electrical characteristics 4. For operation with voltage higher than Min (VDD, VDDA, VDD33USB) +0.3V, the internal Pull-up and Pull-Down resistors must be disabled. 5. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 7.9: Thermal characteristics). 6. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.9: Thermal characteristics). 6.3.
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Electrical characteristics 6.3.4 STM32H743xI Embedded reset and power control block characteristics The parameters given in Table 26 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 23: General operating conditions. Table 26.
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STM32H743xI Electrical characteristics Table 26. Reset and power control block characteristics (continued) Symbol Parameter Conditions Min Typ Max VAVM_0 Analog voltage detector for VDDA threshold 0 Rising edge 1.66 1.71 1.76 1.56 1.61 1.66 VAVM_1 Analog voltage detector for VDDA threshold 1 Rising edge 2.06 2.12 2.19 1.96 2.02 2.08 VAVM_2 Analog voltage detector for VDDA threshold 2 Rising edge 2.42 2.50 2.58 2.35 2.42 2.
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Electrical characteristics STM32H743xI Table 27. Embedded reference voltage (continued) Symbol Parameter Conditions Min Typ Max VREFINT_DIV1 1/4 reference voltage - - 25 - VREFINT_DIV2 1/2 reference voltage - - 50 - VREFINT_DIV3 3/4 reference voltage - - 75 - 1. The shortest sampling time for the application can be determined by multiple iterations. 2. Guaranteed by design. Unit % VREFINT Table 28.
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STM32H743xI Electrical characteristics Table 29. Typical and maximum current consumption in Run mode, code with data processing running from ITCM, regulator ON(1) Symbol Parameter Conditions VOS1 VOS2 All peripherals disabled IDD Supply current in Run mode VOS3 VOS1 All peripherals VOS2 enabled VOS3 Max(2) frcc_c_ck (MHz) Typ TJ = 25°C TJ = 85°C TJ = 105°C TJ = 125°C 400 71 110 210 290 540 300 56 - - - - 300 50 72 170 230 370 216 37 58 150 210 380 200 35.
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Electrical characteristics STM32H743xI Table 30.
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STM32H743xI Electrical characteristics Table 32. Typical consumption in Run mode and corresponding performance versus code position Symbol Parameter Conditions All peripherals disabled, cache ON Supply current in Run mode IDD frcc_c_c (MHz) Coremar k Typ ITCM 400 2012 71 35 FLASH A 400 2012 105 52 AXI SRAM 400 2012 105 52 SRAM1 400 2012 105 52 SRAM4 400 2012 105 ITCM 400 2012 71 FLASH A 400 593 70.5 119 AXI SRAM 400 344 70.5 205 SRAM1 400 472 74.
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Electrical characteristics STM32H743xI Table 35. Typical and maximum current consumption in Stop mode, regulator ON Max(1) Symbol Parameter Flash memory OFF, no IWDG D1Stop, D2Stop, D3Stop IDD(Stop) Conditions Flash memory ON, no IWDG D1Stop, D2Standby, D3Stop Flash memory OFF, no IWDG Flash memory ON, no IWDG D1Standby, D2Stop, D3Stop Flash OFF, no IWDG D1Standby, D2Standby, D3Stop Typ TJ = 25°C TJ = 85°C TJ = 105°C TJ = 125°C SVOS5 1.4 7.2 49 75 140 SVOS4 1.
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STM32H743xI Electrical characteristics Table 37. Typical and maximum current consumption in VBAT mode Conditions Symbol Parameter IDD Supply current in standby mode (VBAT) Max (3 V)(1) Typ Backup SRAM RTC & LSE 1.2 V OFF OFF 0.024 ON OFF 1.4 1.6 1.8 1.8 OFF ON 0.225 0.23 0.25 ON ON 1.95 2.15 2.2 2V 3V 3.4 V TJ = 25°C 0.035 0.062 0.096 0.074 TJ = 85°C TJ = TJ = 105°C 125°C 1.5 4.1 11 3.2 19 42 74 0.31 - - - - 2.35 - - - - Unit µA 1.
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Electrical characteristics STM32H743xI The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. On-chip peripheral current consumption The MCU is placed under the following conditions: • At startup, all I/O pins are in analog input configuration. • All peripherals are disabled unless otherwise mentioned. • The I/O compensation cell is enabled. • fACLK is the system clock. fPCLK = fACLK/4, and fHCLK = fACLK/2.
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STM32H743xI Electrical characteristics Table 38. Peripheral current consumption in Run mode IDD(Typ) Peripheral AHB3 Unit VOS1 VOS2 VOS3 MDMA 8.3 7.6 7 DMA2D 21 20 18 JPEG 24 23 21 FLASH 9.9 9 8.3 FMC registers 0.9 0.9 0.8 FMC kernel 6.1 5.5 5.3 QUADSPI registers 1.5 1.4 1.3 QUADSPI kernel 0.9 0.8 0.7 SDMMC1 registers 8 7.2 6.8 SDMMC1 kernel 2.4 2 1.8 DTCM1 5.7 5 4.5 DTCM2 5.5 4.8 4.3 ITCM 3.2 2.9 2.6 D1SRAM1 7.6 6.8 6.1 Bridge AHB3 7.5 6.
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Electrical characteristics STM32H743xI Table 38. Peripheral current consumption in Run mode (continued) IDD(Typ) Peripheral AHB2 AHB4 APB3 110/226 Downloaded from Arrow.com. Unit VOS1 VOS2 VOS3 DCMI 1.7 1.7 1.7 RNG registers 1.8 1.4 1.2 RNG kernel - 9.6 9.6 SDMMC2 registers 13 12 11 SDMMC2 kernel 2.7 2.5 2.4 D2SRAM1 3.3 3.1 2.8 D2SRAM2 2.9 2.7 2.5 D2SRAM3 1.9 1.8 1.7 Bridge AHB2 0.1 0.1 0.1 GPIOA 1.1 1 0.9 GPIOB 1 0.9 0.9 GPIOC 1.4 1.3 1.
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STM32H743xI Electrical characteristics Table 38. Peripheral current consumption in Run mode (continued) IDD(Typ) Peripheral APB1 Unit VOS1 VOS2 VOS3 TIM2 3.5 3.2 2.9 TIM3 3.4 3.1 2.7 TIM4 2.7 2.5 1.9 TIM5 3.2 2.9 2.5 TIM6 1 0.8 0.7 TIM7 1 0.9 0.7 TIM12 1.7 1.5 1.2 TIM13 1.5 1.3 1 TIM14 1.4 1.3 0.9 LPTIM1 registers 0.7 0.6 0.5 LPTIM1 kernel 2.3 2.1 1.9 WWDG2 0.6 0.4 0.4 SPI2 registers 1.8 1.5 1.2 SPI2 kernel 0.6 0.5 0.5 SPI3 registers 1.5 1.
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Electrical characteristics STM32H743xI Table 38. Peripheral current consumption in Run mode (continued) IDD(Typ) Peripheral APB1 (continued) 112/226 Downloaded from Arrow.com. Unit VOS1 VOS2 VOS3 UART5 registers 1.4 1.4 1 UART5 kernel 3.6 3.2 3.1 I2C1 registers 0.8 0.8 0.6 I2C1 kernel 2 1.8 1.7 I2C2 registers 0.7 0.7 0.4 I2C2 kernel 1.9 1.7 1.6 I2C3 registers 0.9 0.7 0.6 I2C3 kernel 2.1 1.9 1.9 HDMI-CEC registers 0.5 0.3 0.3 DAC1/2 1.4 1.1 0.
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STM32H743xI Electrical characteristics Table 38. Peripheral current consumption in Run mode (continued) IDD(Typ) Peripheral APB2 Unit VOS1 VOS2 VOS3 TIM1 5.1 4.8 4.3 TIM8 5.4 4.9 4.6 USART1 registers 2.7 2.6 2.5 USART1 kernel 0.1 0.1 0.1 USART6 registers 2.6 2.5 2.5 USART6 kernel 0.1 0.1 0.1 SPI1 registers 1.8 1.6 1.6 SPI1 kernel 1 0.8 0.6 SPI4 registers 1.6 1.5 1.5 SPI4 kernel 0.5 0.4 0.4 TIM15 3.1 2.8 2.7 TIM16 2.4 2.1 2.1 TIM17 2.2 2 1.
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Electrical characteristics STM32H743xI Table 38. Peripheral current consumption in Run mode (continued) IDD(Typ) Peripheral APB4 Unit VOS1 VOS2 VOS3 SYSCFG 1 0.7 0.7 LPUART1 registers 1.1 1.1 1.1 LPUART1 kernel 2.6 2.4 2.1 SPI6 registers 1.6 1.5 1.4 SPI6 kernel 0.2 0.2 0.2 I2C4 registers 0.1 0.1 0.1 I2C4 kernel 2.4 2.1 2 LPTIM2 registers 0.5 0.5 0.5 LPTIM2 kernel 2.3 2.1 1.8 LPTIM3 registers 0.5 0.5 0.5 LPTIM3 kernel 2 2.1 1.5 LPTIM4 registers 0.5 0.
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STM32H743xI 6.3.7 Electrical characteristics Wakeup time from low-power modes The wakeup times given in Table 40 are measured starting from the wakeup event trigger up to the first instruction executed by the CPU: • For Stop or Sleep modes: the wakeup event is WFE. • WKUP (PC1) pin is used to wakeup from Standby, Stop and Sleep modes. All timings are derived from tests performed under ambient temperature and VDD=3.3 V. Table 40.
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Electrical characteristics 6.3.8 STM32H743xI External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The external clock signal has to respect the Table 58: I/O static characteristics. However, the recommended clock input waveform is shown in Figure 16. Table 41.
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STM32H743xI Electrical characteristics Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The external clock signal has to respect the Table 58: I/O static characteristics. However, the recommended clock input waveform is shown in Figure 17. Table 42.
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Electrical characteristics STM32H743xI High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 43.
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STM32H743xI Electrical characteristics Figure 18. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 8 MHz resonator CL2 fHSE OSC_IN REXT(1) RF Bias controlled gain OSC_OU T STM32 ai17530b 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator.
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Electrical characteristics Note: STM32H743xI For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 19. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 fLSE OSC32_IN Bias RF controlled gain 32.768 kH z resonator OSC32_OU T CL2 STM32 ai17531b 1.
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STM32H743xI Electrical characteristics 64 MHz high-speed internal RC oscillator (HSI) Table 46. HSI oscillator characteristics(1) Symbol Parameter fHSI HSI frequency TRIM HSI user trimming step DuCy(HSI) Duty Cycle ΔVDD (HSI) HSI oscillator frequency drift over VDD (reference is 3.
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Electrical characteristics STM32H743xI Low-speed internal (LSI) RC oscillator Table 48. LSI oscillator characteristics Symbol fLSI Parameter Conditions LSI frequency Min Typ Max VDD = 3.3 V, TJ = 25 °C (after calibration) 31.4 32 32.6 TJ = –40 to 105 °C, VDD = 1.62 to 3.6 V 29.76 - 33.
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STM32H743xI Electrical characteristics Table 49. Main PLL characteristics(1) (continued) Symbol Parameter Conditions Cycle-to-cycle jitter Jitter Long term jitter IDD(PLL)(3) Min Typ Max VCO = 192 MHz - 134 - VCO = 200 MHz - 134 - VCO = 400 MHz - 76 - VCO = 800 MHz - 39 - Normal mode - ±0.7 - Sigma-delta mode (CKIN = 16 MHz) - ±0.
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Electrical characteristics STM32H743xI Table 51. Flash memory programming (single bank configuration nDBANK=1) Symbol tprog tERASE128KB tME Min(1) Typ Max(1) Program/erase parallelism x 8 - 290 580(2) Program/erase parallelism x 16 - 180 360 Program/erase parallelism x 32 - 130 260 Program/erase parallelism x 64 - 100 200 Program/erase parallelism x 8 - 2 4 Program/erase parallelism x 16 - 1.8 3.
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STM32H743xI 6.3.12 Electrical characteristics EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs.
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Electrical characteristics STM32H743xI Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
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STM32H743xI Electrical characteristics Static latchup Two complementary static tests are required on six parts to assess the latchup performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with JESD78 IC latchup standard. Table 56. Electrical sensitivities Symbol LU 6.3.
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Electrical characteristics 6.3.15 STM32H743xI I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 58: I/O static characteristics are derived from tests performed under the conditions summarized in Table 23: General operating conditions. All I/Os are CMOS and TTL compliant (except for BOOT0). Table 58. I/O static characteristics Symbol Parameter Condition Min Typ Max - - 0.3xVDD - - 0.4xVDD− 0.
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STM32H743xI Electrical characteristics Figure 20. VIL/VIH for all I/Os except BOOT0 3 2.5 V DD Voltage 1.5 TLL requirement: VIHmin = 2 V e OS r , CM ction rodu d in p Teste me quire =0.7 min nt: V IH 2 ulation n sim ased o +0.25 0.47VDD VIHmin= B +0.1 0.4VDD VILmax= 0.3VDD ulation im ax= s V IL n o ent: m Based quirem re S O CM uction, in prod TLL requirement: VILmin = 0.8 V Tested 1 0.5 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
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Electrical characteristics STM32H743xI Output voltage levels Unless otherwise specified, the parameters given in Table 59 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 23: General operating conditions. All I/Os are CMOS and TTL compliant. Table 59. Output voltage characteristics(1) Symbol Parameter Conditions(3) Min Max Unit port(2) Output low level voltage CMOS IIO=8 mA 2.7 V≤ VDD ≤3.
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STM32H743xI Electrical characteristics Output buffer timing characteristics (HSLV option disabled) The HSLV bit of SYSCFG_CCCSR register can be used to optimize the I/O speed when the product voltage is below 2.5 V. Table 60.
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Electrical characteristics STM32H743xI Table 60. Output timing characteristics (HSLV OFF)(1) (continued) Speed Symbol Parameter conditions Min Max C=50 pF, 2.7 V≤VDD≤3.6 V - 85 C=50 pF, 1.62 V≤VDD≤2.7 V(4) - 35 - 110 C=30 pF, 1.62 V≤VDD≤2.7 V - 40 C=10 pF, 2.7 V≤VDD≤3.6 V(4) - 166 C=10 pF, 1.62 V≤VDD≤2.7 V(4) - 100 - 3.8 (4) (4) Fmax(2) Maximum frequency 10 C=30 pF, 2.7 V≤VDD≤3.6 V (4) (4) C=50 pF, 2.7 V≤VDD≤3.6 V (4) C=50 pF, 1.62 V≤VDD≤2.
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STM32H743xI Electrical characteristics Output buffer timing characteristics (HSLV option enabled) Table 61.
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Electrical characteristics 6.3.16 STM32H743xI NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 58: I/O static characteristics). Unless otherwise specified, the parameters given in Table 62 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 23: General operating conditions. Table 62.
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STM32H743xI 6.3.17 Electrical characteristics FMC characteristics Unless otherwise specified, the parameters given in Table 63 to Table 76 for the FMC interface are derived from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage conditions summarized in Table 23: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.
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Electrical characteristics STM32H743xI Figure 22. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms tw(NE) FMC_NE tv(NOE_NE) t w(NOE) t h(NE_NOE) FMC_NOE FMC_NWE tv(A_NE) FMC_A[25:0] t h(A_NOE) Address tv(BL_NE) t h(BL_NOE) FMC_NBL[1:0] t h(Data_NE) t su(Data_NOE) th(Data_NOE) t su(Data_NE) Data FMC_D[15:0] t v(NADV_NE) tw(NADV) FMC_NADV (1) FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE) MS32753V1 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. 136/226 Downloaded from Arrow.
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STM32H743xI Electrical characteristics Table 63. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) Symbol Min Max 2Tfmc_ker_ck − 1 2 Tfmc_ker_ck +1 0 0.5 2Tfmc_ker_ck − 1 2Tfmc_ker_ck + 1 FMC_NOE high to FMC_NE high hold time 0 - FMC_NEx low to FMC_A valid - 0.5 th(A_NOE) Address hold time after FMC_NOE high 0 - tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.
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Electrical characteristics STM32H743xI Figure 23. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms tw(NE) FMC_NEx FMC_NOE tv(NWE_NE) t h(NE_NWE) tw(NWE) FMC_NWE tv(A_NE) FMC_A[25:0] th(A_NWE) Address tv(BL_NE) FMC_NBL[1:0] th(BL_NWE) NBL tv(Data_NE) th(Data_NWE) Data FMC_D[15:0] t v(NADV_NE) tw(NADV) FMC_NADV (1) FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE) MS32754V1 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. Table 65.
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STM32H743xI Electrical characteristics Table 66. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings(1)(2) Symbol Min Max 8Tfmc_ker_ck − 1 8Tfmc_ker_ck + 1 FMC_NWE low time 6Tfmc_ker_ck − 1.5 6Tfmc_ker_ck + 0.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5Tfmc_ker_ck + 13 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4Tfmc_ker_ck+ 13 - tw(NE) tw(NWE) Parameter FMC_NE low time Unit ns 1. Guaranteed by characterization results. 2.
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Electrical characteristics STM32H743xI Table 67. Asynchronous multiplexed PSRAM/NOR read timings(1) Symbol Parameter Min Max 3Tfmc_ker_ck − 1 3Tfmc_ker_ck + 1 2Tfmc_ker_ck 2Tfmc_ker_ck + 0.5 Tfmc_ker_ck − 1 Tfmc_ker_ck + 1 FMC_NOE high to FMC_NE high hold time 0 - FMC_NEx low to FMC_A valid - 0.5 FMC_NEx low to FMC_NADV low 0 0.5 FMC_NADV low time Tfmc_ker_ck − 0.5 Tfmc_ker_ck+1 th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high Tfmc_ker_ck + 0.
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STM32H743xI Electrical characteristics Figure 25. Asynchronous multiplexed PSRAM/NOR write waveforms tw(NE) FMC_ NEx FMC_NOE tv(NWE_NE) t h(NE_NWE) tw(NWE) FMC_NWE th(A_NWE) tv(A_NE) FMC_ A[25:16] Address tv(BL_NE) FMC_ NBL[1:0] th(BL_NWE) NBL t v(A_NE) t v(Data_NADV) Data Address FMC_ AD[15:0] th(Data_NWE) th(AD_NADV) t v(NADV_NE) tw(NADV) FMC_NADV FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE) MS32756V1 Table 69.
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Electrical characteristics STM32H743xI Table 70. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1) Symbol Parameter FMC_NE low time tw(NE) tw(NWE) FMC_NWE low time tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid Min Max 9Tfmc_ker_ck – 1 9Tfmc_ker_ck 7Tfmc_ker_ck – 0.5 7Tfmc_ker_ck + 0.5 6Tfmc_ker_ck + 3 - 4Tfmc_ker_ck - Unit ns 1. Guaranteed by characterization results.
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STM32H743xI Electrical characteristics Figure 26.
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Electrical characteristics STM32H743xI Table 71. Synchronous multiplexed NOR/PSRAM read timings(1) Symbol tw(CLK) Parameter FMC_CLK period td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..
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STM32H743xI Electrical characteristics Figure 27.
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Electrical characteristics STM32H743xI Table 72. Synchronous multiplexed PSRAM write timings(1) Symbol tw(CLK) Parameter FMC_CLK period Min Max 2Tfmc_ker_ck − 1 - - 1 Tfmc_ker_ck + 0.5 - td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2) td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1.
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STM32H743xI Electrical characteristics Figure 28.
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Electrical characteristics STM32H743xI Figure 29. Synchronous non-multiplexed PSRAM write timings tw(CLK) tw(CLK) FMC_CLK td(CLKL-NExL) td(CLKH-NExH) Data latency = 0 FMC_NEx td(CLKL-NADVL) td(CLKL-NADVH) FMC_NADV td(CLKH-AIV) td(CLKL-AV) FMC_A[25:0] td(CLKL-NWEL) td(CLKH-NWEH) FMC_NWE td(CLKL-Data) FMC_D[15:0] td(CLKL-Data) D1 D2 FMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) td(CLKH-NBLH) th(CLKH-NWAITV) FMC_NBL MS32760V1 Table 74.
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STM32H743xI Electrical characteristics NAND controller waveforms and timings Figure 30 through Figure 33 represent synchronous waveforms, and Table 75 and Table 76 provide the corresponding timings. The results shown in this table are obtained with the following FMC configuration: • COM.FMC_SetupTime = 0x01 • COM.FMC_WaitSetupTime = 0x03 • COM.FMC_HoldSetupTime = 0x02 • COM.FMC_HiZSetupTime = 0x01 • ATT.FMC_SetupTime = 0x01 • ATT.FMC_WaitSetupTime = 0x03 • ATT.
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Electrical characteristics STM32H743xI Figure 31. NAND controller waveforms for write access FMC_NCEx ALE (FMC_A17) CLE (FMC_A16) th(NWE-ALE) td(ALE-NWE) FMC_NWE FMC_NOE (NRE) th(NWE-D) tv(NWE-D) FMC_D[15:0] MS32768V1 Figure 32. NAND controller waveforms for common memory read access FMC_NCEx ALE (FMC_A17) CLE (FMC_A16) th(NOE-ALE) td(ALE-NOE) FMC_NWE tw(NOE) FMC_NOE tsu(D-NOE) th(NOE-D) FMC_D[15:0] MS32769V1 150/226 Downloaded from Arrow.com.
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STM32H743xI Electrical characteristics Figure 33. NAND controller waveforms for common memory write access FMC_NCEx ALE (FMC_A17) CLE (FMC_A16) td(ALE-NOE) tw(NWE) th(NOE-ALE) FMC_NWE FMC_N OE td(D-NWE) tv(NWE-D) th(NWE-D) FMC_D[15:0] MS32770V1 Table 75. Switching characteristics for NAND Flash read cycles(1) Symbol tw(N0E) Parameter FMC_NOE low width Min Max 4Tfmc_ker_ck − 0.5 4Tfmc_ker_ck + 0.
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Electrical characteristics STM32H743xI SDRAM waveforms and timings In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period, with the following FMC_SDCLK maximum values: • For 1.8 V
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STM32H743xI Electrical characteristics Table 78. LPSDR SDRAM read timings(1) Symbol Parameter Min Max tW(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck − 1 2Tfmc_ker_ck + 0.5 tsu(SDCLKH_Data) Data input setup time 2 - th(SDCLKH_Data) Data input hold time 1.5 - td(SDCLKL_Add) Address valid time - 2.5 td(SDCLKL_SDNE) Chip select valid time - 2.5 th(SDCLKL_SDNE) Chip select hold time 0 - td(SDCLKL_SDNRAS SDNRAS valid time - 0.
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Electrical characteristics STM32H743xI Table 79. SDRAM write timings(1) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck − 1 2Tfmc_ker_ck + 0.5 td(SDCLKL _Data) Data output valid time - 3 th(SDCLKL _Data) Data output hold time 0 - td(SDCLKL_Add) Address valid time - 1.5 td(SDCLKL_SDNWE) SDNWE valid time - 1.5 th(SDCLKL_SDNWE) SDNWE hold time 0.5 - td(SDCLKL_ SDNE) Chip select valid time - 1.5 th(SDCLKL-_SDNE) Chip select hold time 0.
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STM32H743xI 6.3.18 Electrical characteristics Quad-SPI interface characteristics Unless otherwise specified, the parameters given in Table 81 and Table 82 for Quad-SPI are derived from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage conditions summarized in Table 23: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Measurement points are done at CMOS levels: 0.
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Electrical characteristics STM32H743xI Table 82. Quad SPI characteristics in DDR mode Symbol Fck1/t(CK) tw(CKH) Parameter Quad-SPI clock frequency Conditions Min Typ Max 2.7 V
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STM32H743xI 6.3.19 Electrical characteristics Delay block (DLYB) characteristics Unless otherwise specified, the parameters given in Table 84 for the delay block are derived from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage summarized in Table 23: General operating conditions. Table 83. Dynamics characteristics: Delay Block characteristics 6.3.
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Electrical characteristics STM32H743xI Table 84. ADC characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit fADC = 36 MHz - - 3.
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STM32H743xI Electrical characteristics Table 85.
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Electrical characteristics Note: STM32H743xI ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.
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STM32H743xI Electrical characteristics Figure 39. Typical connection diagram using the ADC STM32 VDD RAIN(1) AINx VAIN Cparasitic Sample and hold ADC converter VT 0.6 V RADC(1) VT 0.6 V IL±1 μA 12-bit converter C ADC(1) ai17534b 1. Refer to Table 84 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy.
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Electrical characteristics STM32H743xI General PCB design guidelines Power supply decoupling should be performed as shown in Figure 40 or Figure 41, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 40. Power supply and reference decoupling (VREF+ not connected to VDDA) STM32 VREF+ (1) 1 μF // 10 nF VDDA 1 μF // 10 nF VSSA/VREF+ (1) ai17535c 1.
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STM32H743xI 6.3.21 Electrical characteristics DAC electrical characteristics Table 86. DAC characteristics Symbol Parameter Conditions Min Typ Max VDDA Analog supply voltage - 1.8 3.3 3.6 VREF+ Positive reference voltage - 1.80 - VDDA VREF- Negative reference voltage - - VSSA - connected to VSSA 5 - - connected to VDDA 25 - - 10.3 13 16 VDD = 2.7 V - - 1.6 VDD = 2.0 V - - 2.6 VDD = 2.7 V - - 17.
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Electrical characteristics STM32H743xI Table 86.
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STM32H743xI Electrical characteristics Table 87. DAC accuracy(1) (continued) Symbol Parameter OffsetCal Offset error at code 0x800 after factory calibration Gain Gain Conditions error(5) DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 ㏀ VREF+ = 3.6 V Min Typ Max - - ±5 Unit LSB VREF+ = 1.
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Electrical characteristics 6.3.22 STM32H743xI Voltage reference buffer characteristics Table 88. VREFBUF characteristics(1) Symbol Parameter Conditions Normal mode VDDA Analog supply voltage Degraded mode Normal mode VREFBUF _OUT Voltage Reference Buffer Output Min Typ Max VSCALE = 000 2.8 3.3 3.6 VSCALE = 001 2.4 - 3.6 VSCALE = 010 2.1 - 3.6 VSCALE = 011 1.8 - 3.6 VSCALE = 000 1.62 - 2.80 VSCALE = 001 1.62 - 2.40 VSCALE = 010 1.62 - 2.10 VSCALE = 011 1.
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STM32H743xI Electrical characteristics Table 88. VREFBUF characteristics(1) (continued) Symbol tSTART IINRUSH IDDA(VRE FBUF) Parameter Conditions Start-up time Typ Max CL=0.5 µF - - 300 - CL=1 µF - - 500 - CL=1.5 µF - - 650 - - 8 - Control of maximum DC current drive on VREFBUF_OUT during startup phase(3) - VREFBUF consumption from VDDA Min Unit µs mA ILOAD = 0 µA - - 15 25 ILOAD = 500 µA - - 16 30 ILOAD = 4 mA - - 32 50 µA 1. Guaranteed by design. 2.
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Electrical characteristics 6.3.24 STM32H743xI VBAT monitoring characteristics Table 91. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for VBAT - 26 - KΩ Q Ratio on VBAT measurement - 4 - - –10 - +10 % (1) Error on Q Er tS_vbat(1) ADC sampling time when reading VBAT input µs 1. Guaranteed by design. Table 92. VBAT charging characteristics Symbol RBC 6.3.
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STM32H743xI 6.3.26 Electrical characteristics Comparator characteristics Table 94. COMP characteristics(1) Symbol Conditions Min Typ Max Analog supply voltage - 1.62 3.3 3.6 Comparator input voltage range - 0 - VDDA VBG(2) Scaler input voltage - Refer to VREFINT VSC Scaler offset voltage - - ±5 ±10 BRG_EN=0 (bridge disable) - 0.2 0.3 BRG_EN=1 (bridge enable) - 0.
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Electrical characteristics 6.3.27 STM32H743xI Operational amplifiers characteristics Table 95. OPAMP characteristics(1) Symbol Parameter Conditions Min Typ Max Unit VDDA Analog supply voltage Range - 2 3.3 3.6 CMIR Common Mode Input Range - 0 - VDDA 25°C, no load on output - - ±1.5 All voltages and temperature, no load - - ±2.5 - - ±3.0 - TRIMOFFSETP Offset trim step at low common input voltage TRIMLPOFFSETP (0.1*V DDA) - - 1.1 1.
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STM32H743xI Electrical characteristics Table 95. OPAMP characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit VDDA −100 mV - - Iload=max or RLOAD=min , Input at 0 V - - 100 Normal mode CLOAD ≤ 50pf, RLOAD ≥ 4 kΩ(2), follower configuration - 0.8 3.2 High speed CLOAD ≤ 50pf, RLOAD ≥ 4 kΩ(2), follower configuration - 0.9 2.
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Electrical characteristics STM32H743xI Table 95. OPAMP characteristics(1) (continued) Symbol en IDDA(OPAMP) Parameter Conditions at 1 KHz Voltage noise density at 10 KHz OPAMP consumption from VDDA Normal mode Highspeed mode output loaded with 4 kΩ no Load, quiescent mode, follower Min Typ Max - 140 - - 55 - - 570 1000 - 610 1200 2. RLOAD is the resistive load connected to VSSA or to VDDA. 3. R2 is the internal resistance between the OPAMP output and th OPAMP inverting input.
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STM32H743xI 6.3.28 Electrical characteristics Digital filter for Sigma-Delta Modulators (DFSDM) characteristics Unless otherwise specified, the parameters given in Table 96 for DFSDM are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage summarized in Table 23: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.
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Electrical characteristics STM32H743xI Table 96. DFSDM measured timing 1.62-3.6 V (continued) Symbol Parameter Conditions Min Typ Max twh(CKIN) twl(CKIN) Input clock high and low time SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.62 < VDD < 3.6 V TCKIN/2 - 0.5 TCKIN/2 - tsu Data input setup time SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.62 < VDD < 3.
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STM32H743xI Electrical characteristics DFSDM_CKINy DFSDM_DATINy DFSDM_CKOUT (SPICKSEL=0) tsu th twl twh tr tf tr tf SITP = 00 tsu th SITP = 01 SPICKSEL=3 SPICKSEL=2 SPICKSEL=1 tsu DFSDM_DATINy SPI timing : SPICKSEL = 1, 2, 3 SPI timing : SPICKSEL = 0 Figure 43.
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Electrical characteristics 6.3.
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STM32H743xI 6.3.
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Electrical characteristics STM32H743xI Figure 45. LCD-TFT horizontal timing diagram tCLK LCD_CLK LCD_VSYNC tv(HSYNC) tv(HSYNC) LCD_HSYNC th(DE) tv(DE) LCD_DE tv(DATA) LCD_R[0:7] LCD_G[0:7] LCD_B[0:7] Pixel Pixel 1 2 Pixel N th(DATA) HSYNC Horizontal width back porch Active width Horizontal back porch One line MS32749V1 Figure 46.
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STM32H743xI 6.3.31 Electrical characteristics Timer characteristics The parameters given in Table 99 are guaranteed by design. Refer to Section 6.3.15: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 99.
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Electrical characteristics 6.3.32 STM32H743xI Communications interfaces I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev. 03 for: • Standard-mode (Sm): with a bit rate up to 100 kbit/s • Fast-mode (Fm): with a bit rate up to 400 kbit/s. • Fast-mode Plus (Fm+): with a bit rate up to 1Mbit/s.
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STM32H743xI Electrical characteristics SPI interface characteristics Unless otherwise specified, the parameters given in Table 102 for the SPI interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 23: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.
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Electrical characteristics STM32H743xI Table 102. SPI dynamic characteristics(1) (continued) Symbol tsu(MI) tsu(SI) Parameter Data input setup time th(MI) Data input hold time th(SI) Conditions Min Typ Max Master mode 1 - - Slave mode 2 - - Master mode 2 - - Slave mode 1 - - ta(SO) Data output access time Slave mode 9 13 27 tdis(SO) Data output disable time Slave mode 0 1 5 Slave mode, 2.7 V≤VDD≤3.6 V - 11.5 16 Slave mode 1.62 V≤VDD≤3.
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STM32H743xI Electrical characteristics Figure 48. SPI timing diagram - slave mode and CPHA = 1(1) NSS input tc(SCK) tsu(NSS) tw(SCKH) ta(SO) tw(SCKL) tf(SCK) th(NSS) SCK input CPHA=1 CPOL=0 CPHA=1 CPOL=1 MISO output tv(SO) th(SO) First bit OUT tsu(SI) tr(SCK) Next bits OUT tdis(SO) Last bit OUT th(SI) First bit IN MOSI input Next bits IN Last bit IN MSv41659V1 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. Figure 49.
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Electrical characteristics STM32H743xI I2S interface characteristics Unless otherwise specified, the parameters given in Table 103 for the I2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 23: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.
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STM32H743xI Electrical characteristics Figure 50. I2S slave timing diagram (Philips protocol)(1) 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 51. I2S master timing diagram (Philips protocol)(1) 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. DocID030538 Rev 3 185/226 196 Downloaded from Arrow.com.
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Electrical characteristics STM32H743xI SAI characteristics Unless otherwise specified, the parameters given in Table 104 for SAI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 23: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C=30 pF • Measurement points are performed at CMOS levels: 0.5VDD Refer to Section 6.3.
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STM32H743xI Electrical characteristics Figure 52. SAI master timing waveforms 1/fSCK SAI_SCK_X th(FS) SAI_FS_X (output) tv(FS) tv(SD_MT) SAI_SD_X (transmit) th(SD_MT) Slot n tsu(SD_MR) Slot n+2 th(SD_MR) SAI_SD_X (receive) Slot n MS32771V1 Figure 53.
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Electrical characteristics STM32H743xI Figure 54.
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STM32H743xI Electrical characteristics Table 106. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V(1)(2) Symbol Parameter Conditions Min Typ Max 2 - - 1.5 - - - 1 2 0 - - Unit CMD, D inputs (referenced to CK) in SD default mode tISUD Input setup time SD tIHD Input hold time SD fPP =25 MHz ns CMD, D outputs (referenced to CK) in SD default mode tOVD Output valid default time SD tOHD Output hold default time SD fPP =25 MHz ns 1.
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Electrical characteristics STM32H743xI Figure 55. SDIO high-speed mode Figure 56. SD default mode Figure 57. DDR mode tr(CK) t(CK) tw(CKH) tw(CKL) tf(CK) Clock tvf(OUT) Data output thr(OUT) D0 tvr(OUT) D1 D2 thf(OUT) D3 tsf(IN) thf(IN) Data input D0 D1 D4 D5 tsr(IN) thr(IN) D2 D3 D4 D5 MSv36879V1 CAN (controller area network) interface Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate function characteristics (FDCANx_TX and FDCANx_RX).
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STM32H743xI Electrical characteristics USB OTG_FS characteristics The USB interface is fully compliant with the USB specification version 2.0 and is USB-IF certified (for Full-speed device operation). Table 108. USB OTG_FS electrical characteristics Symbol Parameter Condition Min Typ Max Unit USB transceiver operating voltage - 3.0(1) - 3.
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Electrical characteristics STM32H743xI Figure 58.
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STM32H743xI Electrical characteristics Figure 59. Ethernet SMI timing diagram tMDC ETH_MDC td(MDIO) ETH_MDIO(O) tsu(MDIO) th(MDIO) ETH_MDIO(I) MS31384V1 Table 111 gives the list of Ethernet MAC signals for the RMII and Figure 60 shows the corresponding timing diagram. Table 111. Dynamics characteristics: Ethernet MAC signals for RMII(1) Symbol Parameter Min Typ Max tsu(RXD) Receive data setup time 2 - - tih(RXD) Receive data hold time 3 - - tsu(CRS) Carrier sense setup time 2.
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Electrical characteristics STM32H743xI Table 112. Dynamics characteristics: Ethernet MAC signals for MII(1) Symbol Parameter Min Typ Max tsu(RXD) Receive data setup time 2 - - tih(RXD) Receive data hold time 3 - - tsu(DV) Data valid setup time 1.5 - - tih(DV) Data valid hold time 1 - - tsu(ER) Error setup time 1.5 - - tih(ER) Error hold time 0.5 - - td(TXEN) Transmit enable valid delay time 4.5 6.5 11 td(TXD) Transmit data valid delay time 7 7.5 15 Unit ns 1.
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STM32H743xI Electrical characteristics Table 113. Dynamics characteristics: JTAG characteristics Symbol Parameter Fpp 1/tc(TCK) TCK clock frequency Conditions Min Typ Max 2.7 V
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Electrical characteristics STM32H743xI Figure 62. JTAG timing diagram tc(TCK) TCK tsu(TMS/TDI) th(TMS/TDI) tw(TCKL) tw(TCKH) TDI/TMS tov(TDO) toh(TDO) TDO MSv40458V1 Figure 63. SWD timing diagram tc(SWCLK) SWCLK tsu(SWDIO) th(SWDIO) twSWCLKL) tw(SWCLKH) SWDIO (receive) tov(SWDIO) toh(SWDIO) SWDIO (transmit) MSv40459V1 196/226 Downloaded from Arrow.com.
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STM32H743xI 7 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at www.st.com. ECOPACK® is an ST trademark. 7.1 LQFP100 package information Figure 64. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline 0.
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Package information STM32H743xI Table 115. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.
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STM32H743xI Package information Figure 65. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint 75 51 76 50 0.5 0.3 16.7 14.3 100 26 1.2 25 1 12.3 16.7 ai14906c 1. Dimensions are expressed in millimeters.* DocID030538 Rev 3 199/226 224 Downloaded from Arrow.com.
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Package information STM32H743xI Device marking for LQFP100 The following figure gives an example of topside marking versus pin 1 position identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 66. LQFP100 marking example (package top view) Product identification(1) ES32H743VIT6 R Revision code Date code Y WW Pin 1 indentifier MSv46104V1 1.
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STM32H743xI 7.2 Package information TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package information ddd C Figure 67. TFBGA100, 8 × 8 × 0.8 mm thin fine-pitch ball grid array package outline SEATING PLANE B A1 ball index A1 ball area identifier D1 e A A2 A1 C D F E E1 G A B C D E F G H J K e A 10 9 8 7 6 5 4 3 2 1 BOTTOM VIEW b (100 BALLS) eee C A B fff C TOP VIEW A08Q_ME_V1 1. Drawing is not to scale. Table 116. TFBGA100, 8 x 8 × 0.
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Package information STM32H743xI Table 116. TFBGA100, 8 x 8 × 0.8 mm thin fine-pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max D 7.850 8.000 8.150 0.3091 0.3150 0.3209 D1 - 7.200 - 0.2835 - E 7.850 8.000 8.150 0.3091 0.3150 0.3209 E1 - 7.200 - - 0.2835 - e - 0.800 - - 0.0315 - F - 0.400 - - 0.0157 - G - 0.400 - - 0.0157 - ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.
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STM32H743xI Package information Table 117. TFBGA100 recommended PCB design rules (0.8 mm pitch BGA) Dimension Recommended values Pitch 0.8 Dpad 0.400 mm Dsm 0.470 mm typ (depends on the soldermask registration tolerance) Stencil opening 0.400 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.120 mm Device marking for TFBGA100 The following figure gives an example of topside marking versus pin 1 position identifier location.
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Package information 7.3 STM32H743xI LQFP144 package information Figure 70. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline SEATING PLANE c A1 A2 A C 0.25 mm GAUGE PLANE D L D1 K A1 ccc C L1 D3 108 73 109 E 37 144 PIN 1 E1 E3 b 72 1 36 IDENTIFICATION e 1A_ME_V4 1. Drawing is not to scale. 204/226 Downloaded from Arrow.com.
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STM32H743xI Package information Table 118. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.8740 D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 - 17.500 - - 0.
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Package information STM32H743xI Figure 71. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint 108 109 73 1.35 72 0.35 0.5 19.9 17.85 22.6 144 37 1 36 19.9 22.6 ai14905e 1. Dimensions are expressed in millimeters. 206/226 Downloaded from Arrow.com.
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STM32H743xI Package information Device marking for LQFP144 The following figure gives an example of topside marking versus pin 1 position identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 72. LQFP144 marking example (package top view) Revision code R Product identification(1) ES32H743ZIT6 Date code Y WW Pin 1 identifier MSv46106V1 1.
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Package information 7.4 STM32H743xI UFBGA169 package information Figure 73. UFBGA169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package outline Z Seating plane A2 A4 ddd Z A A3 A1 b SIDE VIEW A1 ball identifier A1 ball index area X E E1 e F A F D D1 e Y N 13 1 BOTTOM VIEW TOP VIEW Øb (169 balls) Ø eee M Z X Y Ø fff M Z A0YV_ME_V2 1. Drawing is not in scale. Table 119. UFBGA169 - 169-pin, 7 x 7 mm, 0.
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STM32H743xI Package information Table 119. UFBGA169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. F 0.450 0.500 0.550 0.0177 0.0197 0.0217 ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. 7.5 LQFP176 package information Figure 74.
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Package information STM32H743xI Table 120. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package mechanical data Dimensions Ref. Inches(1) Millimeters Min. Typ. Max. Min. Typ. Max. A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 - 1.450 0.0531 - 0.0571 b 0.170 - 0.270 0.0067 - 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 23.900 - 24.100 0.9409 - 0.9488 HD 25.900 - 26.100 1.0197 - 1.0276 ZD - 1.250 - - 0.0492 - E 23.
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STM32H743xI Package information Figure 75. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package recommended footprint 1.2 1 176 133 132 0.5 21.8 26.7 0.3 44 45 89 88 1.2 21.8 26.7 1T_FP_V1 1. Dimensions are expressed in millimeters. DocID030538 Rev 3 211/226 224 Downloaded from Arrow.com.
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Package information STM32H743xI Device marking for LQFP176 The following figure gives an example of topside marking versus pin 1 position identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 76. LQFP176 marking example (package top view) Product identification(1) ES32H743IIT6 Y WW Revision code Date code R Pin 1identifier MSv46108V1 1.
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STM32H743xI 7.6 Package information LQFP208 package information Figure 77. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package outline SEATING PLANE c A1 A A2 C ccc C 0.25 mm A1 GAUGE PLANE K L D L1 D1 D3 105 156 104 208 PIN 1 IDENTIFICATION E E3 E1 b 157 53 1 52 e UH_ME_V2 1. Drawing is not to scale. DocID030538 Rev 3 213/226 224 Downloaded from Arrow.com.
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Package information STM32H743xI Table 121. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 29.800 30.000 30.200 1.1811 1.1732 1.1890 D1 27.800 28.000 28.200 1.1024 1.0945 1.1102 D3 - 25.
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STM32H743xI Package information Figure 78. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package recommended footprint 208 157 0.5 30.7 28.3 1.25 156 0.3 1 52 105 53 104 1.2 25.8 30.7 UH_FP_V2 1. Dimensions are expressed in millimeters. DocID030538 Rev 3 215/226 224 Downloaded from Arrow.com.
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Package information STM32H743xI Device marking for LQFP208 The following figure gives an example of topside marking versus pin 1 position identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 79. LQFP208 marking example (package top view) Revision code R Product identification(1) ES32H743BIT6 Date code Y WW Pin 1 identifier MSv46110V1 1.
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STM32H743xI 7.7 Package information UFBGA176+25 package information Figure 80. UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package outline C Seating plane A4 ddd C A3 A2 A1 b e A A1 ball identifier E1 A1 ball index area A E Z A Z D1 D e B R 15 1 BOTTOM VIEW Øb (176 + 25 balls) TOP VIEW Ø eee M C A B Ø fff M C A0E7_ME_V8 1. Drawing is not to scale. Table 122. UFBGA176+25 - ball, 10 x 10 mm, 0.
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Package information STM32H743xI Table 122. UFBGA176+25 - ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 81. UFBGA176+25 - 201-ball, 10 x 10 mm, 0.
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STM32H743xI Package information Device marking for UFBGA176+25 The following figure gives an example of topside marking versus pin 1 position identifier location. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 82. UFBGA176+25 marking example (package top view) Revision code R Product identification(1) ES32H743II Date code Y WW Ball A1identifier MSv46112V1 1.
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Package information 7.8 STM32H743xI TFBGA240+25 package information TFBGA265 package information is preliminary information which are subject to change. ddd C Figure 83. TFBGA240+25 - 265 pin, 14x14 mm, 0.8 mm pitch, fine pitch ball grid array package outline A1 A C A2 SEATING PLANE A1 ball identifier D1 D e E1 E G A e S 1 17 F BOTTOM VIEW b (240 + 25 balls) TOP VIEW A07U_ME_V1 1. Dimensions are expressed in millimeters. 220/226 Downloaded from Arrow.com.
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STM32H743xI Package information Table 124. TFBGA240+25 - 265 pin, 14x14 mm, 0.8 mm pitch, fine pitch ball grid array mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.100 - - 0.0433 A1 0.150 - - 0.0059 - - A2 - 0.760 - - 0.0299 - b 0.350 0.400 0.450 0.0138 0.0157 0.0177 D 13.850 14.000 14.150 0.5453 0.5512 0.5571 D1 - 12.800 - - 0.5039 - E 13.850 14.000 14.150 0.5453 0.5512 0.5571 E1 - 12.800 - - 0.5039 - e - 0.
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Package information STM32H743xI Table 125. TFBGA240+25, 265 pin recommended PCB design rules (0.8 mm pitch) Dimension Recommended values Pitch 0.8 mm Dpad 0.325 mm Dsm 0.425 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.250 mm Stencil thickness 0.100 mm Device marking for TFBGA240+25 The following figure gives an example of topside marking versus pin 1 position identifier location.
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STM32H743xI 7.9 Package information Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max × ΘJA) Where: • TA max is the maximum ambient temperature in ° C, • ΘJA is the package junction-to-ambient thermal resistance, in ° C/W, • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), • PINT max is the product of IDD and VDD, expressed in Watts.
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Ordering information 8 STM32H743xI Ordering information Table 127. STM32H743xI ordering information scheme Example: STM32 H 743 V I T 6 TR Device family STM32 = Arm-based 32-bit microcontroller Product type H = High performance Device subfamily 743 = STM32H7x3 line Pin count V = 100 pins Z = 144 pins A = 169 pins I = 176 pins/balls B = 208 pins X = 240 balls Flash memory size I = 2 Mbytes Package T = LQFP K = UFBGA pitch 0.65 mm I = UFBGA pitch 0.
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STM32H743xI 9 Revision history Revision history Table 128. Document revision history Date Revision 22-Jun-2017 1 Initial release. 2 Updated list of features. Changed datasheet status to “production data”. Added UFBGA169 and TFBGA100 packages and well as notes related their status on cover page and in Table 2: STM32H743xI features and peripheral counts. Differentiated number of GPIOs for each package in Table 2: STM32H743xI features and peripheral counts.
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