Datasheet

Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx
30/255 DocID029041 Rev 6
option bytes. The device remains in reset mode when V
DD
is below a specified threshold,
V
POR/PDR
or V
BOR
, without the need for an external reset circuit.
The device also features an embedded programmable voltage detector (PVD) that monitors
the V
DD
/V
DDA
power supply and compares it to the V
PVD
threshold. An interrupt can be
generated when V
DD
/V
DDA
drops below the V
PVD
threshold and/or when V
DD
/V
DDA
is
higher than the V
PVD
threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
2.18.2 Internal reset OFF
This feature is available only on packages featuring the PDR_ON pin. The internal power-on
reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin.
An external power supply supervisor should monitor V
DD
and NRST and should maintain
the device in reset mode as long as V
DD
is below a specified threshold. PDR_ON should be
connected to V
SS
. Refer to Figure 6: Power supply supervisor interconnection with internal
reset OFF.
Figure 6. Power supply supervisor interconnection with internal reset OFF
The V
DD
specified threshold, below which the device must be maintained under reset, is
1.7
V (see Figure 7).
A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no more supported:
• The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled
• The brownout reset (BOR) circuitry must be disabled
• The embedded programmable voltage detector (PVD) is disabled
• V
BAT
functionality is no more available and V
BAT
pin should be connected to V
DD
.
All the packages, except for the LQFP100, allow to disable the internal reset through the
PDR_ON signal when connected to V
SS
.
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