Datasheet

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STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview
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The devices embed two dedicated PLL (PLLI2S and PLLSAI) which allow to achieve audio
class performance. In this case, the I
2
S and SAI master clock can generate all standard
sampling frequencies from 8
kHz to 192 kHz.
2.16 Boot modes
At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option
bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF
which includes:
• All Flash address space mapped on ITCM or AXIM interface
• All RAM address space: ITCM, DTCM RAMs and SRAMs mapped on AXIM interface
• The System memory bootloader
The boot loader is located in system memory. It is used to reprogram the Flash memory
through a serial interface. Refer to STM32 microcontroller system memory boot mode
application note (AN2606) for details.
2.17 Power supply schemes
• V
DD
= 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when
enabled), provided externally through V
DD
pins.
• V
SSA
, V
DDA
= 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset
blocks, RCs and PLL. V
DDA
and V
SSA
must be connected to V
DD
and V
SS
, respectively.
• V
BAT
= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when V
DD
is not present.
Note: V
DD
/V
DDA
minimum value of 1.7 V is obtained when the internal reset is OFF (refer to
Section 2.18.2: Internal reset OFF). Refer to Table 3: Voltage regulator configuration mode
versus device operating mode to identify the packages supporting this option.
• V
DDSDMMC
can be connected either to V
DD
or an external independent power supply
(1.8 to 3.6V) for SDMMC2 pins (clock, command, and 4-bit data). For example, when
the device is powered at 1.8V, an independent power supply 2.7V can be connected to
V
DDSDMMC
.When the V
DDSDMMC
is connected to a separated power supply, it is
independent from V
DD
or V
DDA
but it must be the last supply to be provided and the first
to disappear. The following conditions V
DDSDMMC
must be respected:
– During the power-on phase (V
DD
< V
DD_MIN
), V
DDSDMMC
should be always lower
than V
DD
– During the power-down phase (V
DD
< V
DD_MIN
), V
DDSDMMC
should be always
lower than V
DD
–The V
DDSDMMC
rising and falling time rate specifications must be respected
– In operating mode phase, V
DDSDMMC
could be lower or higher than V
DD:
All associated GPIOs powered by V
DDSDMMC
are operating between
V
DDSDMMC_MIN
and V
DDSDMMC_MAX.
• V
DDUSB
can be connected either to V
DD
or an external independent power supply (3.0
to 3.6V) for USB transceivers (refer to Figure 4 and Figure 5). For example, when the
device is powered at 1.8V, an independent power supply 3.3V can be connected to
V
DDUSB
. When the V
DDUSB
is connected to a separated power supply, it is independent
from V
DD
or V
DDA
but it must be the last supply to be provided and the first to
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