Datasheet

DocID029041 Rev 6 23/255
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview
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2.7 DMA controller (DMA)
The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. The configuration is made by software and the transfer sizes
between the source and the destination are independent.
The DMA can be used with the main peripherals:
• SPI and I
2
S
• I
2
C
• USART
• General-purpose, basic and advanced-control timers TIMx
• DAC
• SDMMC
• Camera interface (DCMI)
• ADC
• SAI
• SPDIFRX
• Quad-SPI
• HDMI-CEC
• JPEG codec
• DFSDM1
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