Datasheet
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx
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5.3.34 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics
Unless otherwise specified, the parameters given in Table 123 for DFSDM are derived from
tests performed under the ambient temperature, f
PCLK2
frequency and V
DD
supply voltage
summarized in
Table 18, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30pF
• Measurement points are done at CMOS levels: 0.5 x VDD
Refer to Section 5.3.20: I/O port characteristics for more details on the input/output alternate
function characteristics (DFSDM1_CKINx, DFSDM1_DATINx, DFSDM1_CKOUT for
DFSDM1).
Table 123. DFSDM measured timing 1.71-3.6V
Symbol Parameter Conditions Min Typ Max Unit
f
DFSDMCLK
DFSDM clock 1.71 < V
DD
< 3.6 V - - f
SYSCLK
MHz
f
CKIN
(1/T
CKIN
)
Input clock
frequency
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.71 < V
DD
< 3.6 V
--
20
(f
DFSDMCLK
/4)
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
2.7 < V
DD
< 3.6 V
--
20
(f
DFSDMCLK
/4)
SPI mode (SITP[1:0]=0,1),
Internal clock mode
(SPICKSEL[1:0]
≠0),
1.71 < V
DD
< 3.6 V
--
20
(f
DFSDMCLK
/4)
SPI mode (SITP[1:0]=0,1),
Internal clock mode
(SPICKSEL[1:0]≠0),
2.7 < V
DD
< 3.6 V
--
20
(f
DFSDMCLK
/4)
f
CKOUT
Output clock
frequency
1.71 < V
DD
< 3.6 V - - 20
DuCy
CKOUT
Output clock
frequency duty
cycle
1.71 < V
DD
< 3.6 V 45 50 55 %
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