Datasheet
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STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics
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5.3.31 Quad-SPI interface characteristics
Unless otherwise specified, the parameters given in Table 119 and Table 120 for Quad-SPI
are derived from tests performed under the ambient temperature, f
AHB
frequency and V
DD
supply voltage conditions summarized in Table 18: General operating conditions, with the
following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 20 pF
• Measurement points are done at CMOS levels: 0.5 V
DD
Refer to Section 5.3.20: I/O port characteristics for more details on the input/output alternate
function characteristics.
Table 118. LPSDR SDRAM write timings
(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
t
w(SDCLK)
FMC_SDCLK period 2T
HCLK
− 0.5 2T
HCLK
+ 0.5
ns
t
d(SDCLKL _Data
) Data output valid time - 2.5
t
h(SDCLKL _Data)
Data output hold time 0 -
t
d(SDCLKL_Add)
Address valid time - 2.5
t
d(SDCLKL-SDNWE)
SDNWE valid time - 2.5
t
h(SDCLKL-SDNWE)
SDNWE hold time 0 -
t
d(SDCLKL- SDNE)
Chip select valid time - 0.5
t
h(SDCLKL- SDNE)
Chip select hold time 0 -
t
d(SDCLKL-SDNRAS)
SDNRAS valid time - 1.5
t
h(SDCLKL-SDNRAS)
SDNRAS hold time 0 -
t
d(SDCLKL-SDNCAS)
SDNCAS valid time - 1.5
t
d(SDCLKL-SDNCAS)
SDNCAS hold time 0 -
Table 119. Quad-SPI characteristics in SDR mode
(1)
Symbol Parameter Conditions Min Typ Max Unit
Fck1/t(CK)
Quad-SPI clock
frequency
2.7 V
≤ V
DD
<3.6 V
CL=20 pF
--108
MHz
1.71 V<V
DD
<3.6 V
CL=15 pF
--100
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