Datasheet
DocID029041 Rev 6 205/255
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics
220
NAND controller waveforms and timings
Figure 70 through Figure 73 represent synchronous waveforms, and Table 113 and
Table 114 provide the corresponding timings. The results shown in this table are obtained
with the following FMC configuration:
• COM.FMC_SetupTime = 0x01;
• COM.FMC_WaitSetupTime = 0x03;
• COM.FMC_HoldSetupTime = 0x02;
• COM.FMC_HiZSetupTime = 0x01;
• ATT.FMC_SetupTime = 0x01;
• ATT.FMC_WaitSetupTime = 0x03;
• ATT.FMC_HoldSetupTime = 0x02;
• ATT.FMC_HiZSetupTime = 0x01;
• Bank = FMC_Bank_NAND;
• MemoryDataWidth = FMC_MemoryDataWidth_16b;
• ECC = FMC_ECC_Enable;
• ECCPageSize = FMC_ECCPageSize_512Bytes;
• TCLRSetupTime = 0;
• TARSetupTime = 0.
In all timing tables, the T
HCLK
is the HCLK clock period.
Table 112. Synchronous non-multiplexed PSRAM write timings
(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
t
(CLK)
FMC_CLK period 2T
HCLK
− 0.5 -
ns
t
d(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x=0..2) - 2
t
(CLKH-NExH)
FMC_CLK high to FMC_NEx high (x= 0…2) T
HCLK
+ 0.5 -
t
d(CLKL-NADVL)
FMC_CLK low to FMC_NADV low - 0.5
t
d(CLKL-NADVH)
FMC_CLK low to FMC_NADV high 0 -
t
d(CLKL-AV)
FMC_CLK low to FMC_Ax valid (x=16…25) - 2.5
t
d(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid (x=16…25) T
HCLK
-
t
d(CLKL-NWEL)
FMC_CLK low to FMC_NWE low - 1.5
t
d(CLKH-NWEH)
FMC_CLK high to FMC_NWE high T
HCLK
+ 1 -
t
d(CLKL-Data)
FMC_D[15:0] valid data after FMC_CLK low - 3.5
t
d(CLKL-NBLL)
FMC_CLK low to FMC_NBL low - 2
t
d(CLKH-NBLH)
FMC_CLK high to FMC_NBL high T
HCLK
+ 1 -
t
su(NWAIT-CLKH)
FMC_NWAIT valid before FMC_CLK high 2 -
t
h(CLKH-NWAIT)
FMC_NWAIT valid after FMC_CLK high 3.5 -
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