Datasheet

Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx
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5.3.21 NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R
PU
(see Table 66: I/O static characteristics).
Unless otherwise specified, the parameters given in Table 69 are derived from tests
performed under the ambient temperature and V
DD
supply voltage conditions summarized
in
Table 18.
Figure 41. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets. 0.1 uF capacitor must be placed as close as
possible to the chip.
2. The user must ensure that the level on the NRST pin can go below the V
IL(NRST)
max level specified in
Table 69. Otherwise the reset is not taken into account by the device.
Table 69. NRST pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
R
PU
Weak pull-up equivalent resistor
(1)
V
IN
= V
SS
30 40 50 kΩ
V
F(NRST)
(2)
NRST Input filtered pulse - - - 100 ns
V
NF(NRST)
(2)
NRST Input not filtered pulse V
DD
> 2.7 V 300 - - ns
T
NRST_OUT
Generated reset pulse duration Internal Reset source 20 - - µs
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance must be minimum
(~10% order).
2. Guaranteed by design.
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