Datasheet

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STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics
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5.3.11 PLL characteristics
The parameters given in Table 48 and Table 49 are derived from tests performed under
temperature and V
DD
supply voltage conditions summarized in Table 18.
Table 48. Main PLL characteristics
Symbol Parameter Conditions Min Typ Max Unit
f
PLL_IN
PLL input clock
(1)
-0.95
(2)
12.10
MHz
f
PLL_OUT
PLL multiplier output clock - 24 - 216
f
PLL48_OUT
48 MHz PLL multiplier output
clock
- - 48 75
f
VCO_OUT
PLL VCO output - 100 - 432
t
LOCK
PLL lock time
VCO freq = 192 MHz 75 - 200
µs
VCO freq = 432 MHz 100 - 300
Jitter
(3)
Cycle-to-cycle jitter
System clock
216 MHz
RMS - 25 -
ps
peak
to
peak
- ±150 -
Period Jitter
RMS - 15 -
peak
to
peak
- ±200 -
Main clock output (MCO) for
RMII Ethernet
Cycle to cycle at 50 MHz
on 1000 samples
-32 -
Main clock output (MCO) for MII
Ethernet
Cycle to cycle at 25 MHz
on 1000 samples
-40 -
Bit Time CAN jitter
Cycle to cycle at 1 MHz
on 1000 samples
-330 -
I
DD(PLL)
(4)
PLL power consumption on V
DD
VCO freq = 192 MHz
VCO freq = 432 MHz
0.15
0.45
-
0.40
0.75
mA
I
DDA(PLL)
(4)
PLL power consumption on V
DDA
VCO freq = 192 MHz
VCO freq = 432 MHz
0.30
0.55
-
0.40
0.85
mA
1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between PLL and PLLI2S.
2. Guaranteed by design.
3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%.
4. Guaranteed by characterization results.
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