Datasheet
Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx
68/255 DocID029041 Rev 6
D1 13 24 H1 30 33 H1 K13 30 33 H1
PH1-
OSC_OUT
I/O FT
(3)
EVENTOUT OSC_OUT
E1 14 25 J1 31 34 J1 L11 31 34 J1 NRST I/O
RS
T
-- -
F1 15 26 M2 32 35 M2 L12 32 35 M2 PC0 I/O FT -
DFSDM1_CKIN0,
DFSDM1_DATIN4,
SAI2_FS_B,
OTG_HS_ULPI_STP,
FMC_SDNWE, LCD_R5,
EVENTOUT
ADC1_IN10,
ADC2_IN10,
ADC3_IN10
F2 16 27 M3 33 36 M3 L13 33 36 M3 PC1 I/O FT -
TRACED0, DFSDM1_DATIN0,
SPI2_MOSI/I2S2_SD,
SAI1_SD_A, DFSDM1_CKIN4,
ETH_MDC, MDIOS_MDC,
EVENTOUT
ADC1_IN11,
ADC2_IN11,
ADC3_IN11,
RTC_TAMP3/
WKUP3
E2 17 28 M4 34 37 M4 NC 34 37 M4 PC2 I/O FT -
DFSDM1_CKIN1, SPI2_MISO,
DFSDM1_CKOUT,
OTG_HS_ULPI_DIR,
ETH_MII_TXD2, FMC_SDNE0,
EVENTOUT
ADC1_IN12,
ADC2_IN12,
ADC3_IN12
F3 18 29 M5 35 38 L4 NC 35 38 L4 PC3 I/O FT -
DFSDM1_DATIN1,
SPI2_MOSI/I2S2_SD,
OTG_HS_ULPI_NXT,
ETH_MII_TX_CLK,
FMC_SDCKE0, EVENTOUT
ADC1_IN13,
ADC2_IN13,
ADC3_IN13
- - 30 - 36 39 J5 - 36 39 J5 VDD S - - - -
---- --J6---J6 VSS S-- - -
G1 19 31 M1 37 40 M1 M11 37 40 M1 VSSA S - - - -
---N1--N1- --N1VREF-S-- - -
- 2032P13841P1 - 3841P1 VREF+ S - - - -
H1 21 33 R1 39 42 R1 M12 39 42 R1 VDDA S - - - -
G2 22 34 N3 40 43 N3 M13 40 43 N3
PA0-
WKUP
I/O FT
(4)
TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
USART2_CTS, UART4_TX,
SAI2_SD_B, ETH_MII_CRS,
EVENTOUT
ADC1_IN0,
ADC2_IN0,
ADC3_IN0,
WKUP1
Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and
ball definitions (continued)
Pin Number
Pin name (function after reset
Pin type
I/O structure
Notes
Alternate functions
Additional
functions
STM32F765xx
STM32F767xx
STM32F768Ax
STM32F769xx
TFBGA100
LQFP100
LQFP144
UFBGA176
LQFP176
LQFP208
TFBGA216
WLCSP180
(1)
LQFP176
LQFP208
TFBGA216
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