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Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx
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Figure 37. MIPI D-PHY HS/LP clock lane transition timing diagram
Figure 38. MIPI D-PHY HS/LP data lane transition timing diagram
5.3.14 MIPI D-PHY PLL characteristics
The parameters given in Table 54 are derived from tests performed under temperature and 
V
DD
 supply voltage conditions summarized in Table 18.
 
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Table 54. DSI-PLL characteristics
(1)
 
Symbol Parameter Conditions  Min Typ Max Unit
f
PLL_IN
PLL input clock - 4 - 100
MHz
f
PLL_INFIN
PFD input clock - 4 - 25
f
PLL_OUT
PLL multiplier output clock - 31.25 - 500
f
VCO_OUT
PLL VCO output - 500 - 1000
t
LOCK
PLL lock time - - - 200 µs
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