Datasheet
DocID029041 Rev 6 69/255
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description
101
H2 23 35 N2 41 44 N2 J11 41 44 N2 PA1 I/O FT -
TIM2_CH2, TIM5_CH2,
USART2_RTS, UART4_RX,
QUADSPI_BK1_IO3,
SAI2_MCLK_B,
ETH_MII_RX_CLK/ETH_RMII_
REF_CLK, LCD_R2,
EVENTOUT
ADC1_IN1,
ADC2_IN1,
ADC3_IN1
J2 24 36 P2 42 45 P2 J10 42 45 P2 PA2 I/O FT -
TIM2_CH3, TIM5_CH3,
TIM9_CH1, USART2_TX,
SAI2_SCK_B, ETH_MDIO,
MDIOS_MDIO, LCD_R1,
EVENTOUT
ADC1_IN2,
ADC2_IN2,
ADC3_IN2,
WKUP2
- - - F44346K4L104346K4 PH2 I/OFT -
LPTIM1_IN2,
QUADSPI_BK2_IO0,
SAI2_SCK_B, ETH_MII_CRS,
FMC_SDCKE0, LCD_R0,
EVENTOUT
-
- - - G4 44 47 J4 K10 44 47 J4 PH3 I/O FT -
QUADSPI_BK2_IO1,
SAI2_MCLK_B,
ETH_MII_COL, FMC_SDNE0,
LCD_R1, EVENTOUT
-
- - - H4 45 48 H4 N12 45 48 H4 PH4 I/O FT -
I2C2_SCL, LCD_G5,
OTG_HS_ULPI_NXT, LCD_G4,
EVENTOUT
-
- - - J4 46 49 J3 N11 46 49 J3 PH5 I/O FT -
I2C2_SDA, SPI5_NSS,
FMC_SDNWE, EVENTOUT
-
K2 25 37 R2 47 50 R2 M10 47 50 R2 PA3 I/O FT -
TIM2_CH4, TIM5_CH4,
TIM9_CH2, USART2_RX,
LCD_B2, OTG_HS_ULPI_D0,
ETH_MII_COL, LCD_B5,
EVENTOUT
ADC1_IN3,
ADC2_IN3,
ADC3_IN3
J1 26 38 - - 51 K6 J9 - 51 K6 VSS S - - - -
E6 - - L4 48 - L5 -
(5)
48 - L5
BYPASS_
REG
IFT- - -
K1 27 39 K4 49 52 K5 K9 49 52 K5 VDD S - - - -
G3 28 40 N4 50 53 N4 L9 50 53 N4 PA4 I/O TTa -
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART2_CK, SPI6_NSS,
OTG_HS_SOF, DCMI_HSYNC,
LCD_VSYNC, EVENTOUT
ADC1_IN4,
ADC2_IN4,
DAC_OUT1
Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and
ball definitions (continued)
Pin Number
Pin name (function after reset
Pin type
I/O structure
Notes
Alternate functions
Additional
functions
STM32F765xx
STM32F767xx
STM32F768Ax
STM32F769xx
TFBGA100
LQFP100
LQFP144
UFBGA176
LQFP176
LQFP208
TFBGA216
WLCSP180
(1)
LQFP176
LQFP208
TFBGA216
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