Datasheet
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx
198/255 DocID029041 Rev 6
Synchronous waveforms and timings
Figure 66 through Figure 69 represent synchronous waveforms and Table 109 through
Table 112 provide the corresponding timings. The results shown in these tables are
obtained with the following FMC configuration:
• BurstAccessMode = FMC_BurstAccessMode_Enable;
• MemoryType = FMC_MemoryType_CRAM;
• WriteBurst = FMC_WriteBurst_Enable;
• CLKDivision = 1;
• DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
• CL = 30 pF on data and address lines. CL = 10 pF on FMC_CLK unless otherwise
specified.
In all the timing tables, the T
HCLK
is the HCLK clock period.
–For 2.7 V≤ V
DD
≤ 3.6 V, maximum FMC_CLK = 100 MHz at CL=20 pF or 90 MHz at
CL=30 pF (on FMC_CLK).
–For 1.71 V≤ V
DD
<2.7 V, maximum FMC_CLK = 70 MHz at CL=10 pF (on FMC_CLK).
1. Guaranteed by characterization results.
Table 108. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings
(1)
1. Guaranteed by characterization results.
Symbol Parameter Min Max Unit
t
w(NE)
FMC_NE low time 9T
HCLK
– 1 9T
HCLK
+ 1
ns
t
w(NWE)
FMC_NWE low time 7T
HCLK
– 0.5 7T
HCLK
+ 0.5
t
su(NWAIT_NE)
FMC_NWAIT valid before FMC_NEx high 6T
HCLK
+ 2 -
t
h(NE_NWAIT)
FMC_NEx hold time after FMC_NWAIT
invalid
4T
HCLK
– 1 -
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