Datasheet

DocID029041 Rev 6 33/255
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview
53
Figure 8. Regulator OFF
The following conditions must be respected:
• V
DD
should always be higher than V
CAP_1
and V
CAP_2
to avoid current injection
between power domains.
• If the time for V
CAP_1
and V
CAP_2
to reach V
12
minimum value is faster than the time for
V
DD
to reach 1.7 V, then PA0 should be kept low to cover both conditions: until V
CAP_1
and V
CAP_2
reach V
12
minimum value and until V
DD
reaches 1.7 V (see Figure 9).
• Otherwise, if the time for V
CAP_1
and V
CAP_2
to reach V
12
minimum value is slower
than the time for V
DD
to reach 1.7 V, then PA0 could be asserted low externally (see
Figure 10).
• If V
CAP_1
and V
CAP_2
go below V
12
minimum value and V
DD
is higher than 1.7 V, then a
reset must be asserted on PA0 pin.
Note: The minimum value of V
12
depends on the maximum frequency targeted in the application.
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