Datasheet

Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx
144/255 DocID029041 Rev 6
Table 49. PLLI2S characteristics
Symbol Parameter Conditions Min Typ Max Unit
f
PLLI2S_IN
PLLI2S input clock
(1)
-0.95
(2)
12.10
MHz
f
PLLI2SP_OUT
PLLI2S multiplier output clock for
SPDIFRX
- - - 216
f
PLLI2SQ_OUT
PLLI2S multiplier output clock for
SAI
- - - 216
f
PLLI2SR_OUT
PLLI2S multiplier output clock for
I2S
- - - 216
f
VCO_OUT
PLLI2S VCO output - 100 - 432
t
LOCK
PLLI2S lock time
VCO freq = 192 MHz 75 - 200
µs
VCO freq = 432 MHz 100 - 300
Jitter
(3)
Master I2S clock jitter
Cycle to cycle at
12.288 MHz on
48KHz period,
N=432, R=5
RMS - 90 - -
peak
to
peak
- ±280 - ps
Average frequency of
12.288 MHz
N = 432, R = 5
on 1000 samples
-90 -ps
WS I2S clock jitter
Cycle to cycle at 48 KHz
on 1000 samples
-400 - ps
I
DD(PLLI2S)
(4)
PLLI2S power consumption on
V
DD
VCO freq = 192 MHz
VCO freq = 432 MHz
0.15
0.45
-
0.40
0.75
mA
I
DDA(PLLI2S)
(4)
PLLI2S power consumption on
V
DDA
VCO freq = 192 MHz
VCO freq = 432 MHz
0.30
0.55
-
0.40
0.85
mA
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design.
3. Value given with main PLL running.
4. Guaranteed by characterization results.
Table 50. PLLISAI characteristics
Symbol Parameter Conditions Min Typ Max Unit
f
PLLSAI_IN
PLLSAI input clock
(1)
-0.95
(2)
12.10
MHz
f
PLLSAIP_OUT
PLLSAI multiplier output clock
for 48 MHz
- - 48 75
f
PLLSAIQ_OUT
PLLSAI multiplier output clock
for SAI
- - - 216
f
PLLSAIR_OUT
PLLSAI multiplier output clock
for LCD-TFT
- - - 216
f
VCO_OUT
PLLSAI VCO output - 100 - 432
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