Datasheet
DocID029041 Rev 6 37/255
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview
53
Standby mode, the SRAM and register contents are lost except for registers in the
backup domain and the backup SRAM when selected.
The device exits the Standby mode when an external reset (NRST pin), an IWDG reset,
a rising or falling edge on one of the 6 WKUP pins (PA0, PA2, PC1, PC13, PI8, PI11),
or an RTC alarm / wakeup / tamper /time stamp event occurs.
The Standby mode is not supported when the embedded voltage regulator is bypassed
and the 1.2 V domain is controlled by an external power.
2.22 V
BAT
operation
The V
BAT
pin allows to power the device V
BAT
domain from an external battery, an external
supercapacitor, or from V
DD
when no external battery and an external supercapacitor are
present.
V
BAT
operation is activated when V
DD
is not present.
The V
BAT
pin supplies the RTC, the backup registers and the backup SRAM.
Note: When the microcontroller is supplied from V
BAT
, external interrupts and RTC alarm/events
do not exit it from V
BAT
operation.
When the PDR_ON pin is connected to V
SS
(Internal Reset OFF), the V
BAT
functionality is
no more available and the V
BAT
pin should be connected to VDD.
2.23 Timers and watchdogs
The devices include two advanced-control timers, eight general-purpose timers, two basic
timers and two watchdog timers.
All timer counters can be frozen in debug mode.
Table 6 compares the features of the advanced-control, general-purpose and basic timers.
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