Datasheet

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DocID027590 Rev 4 61/227

STM32F745xx STM32F746xx Pinouts and pin description

41 H6 K4 64 P10 74 85 P10 PE11 I/O FT -

TIM1_CH2, SPI4_NSS,

SAI2_SD_B, FMC_D8,

LCD_G3, EVENTOUT

42 J6 L4 65 R10 75 86 R10 PE12 I/O FT -

TIM1_CH3N, SPI4_SCK,

SAI2_SCK_B, FMC_D9,

LCD_B4, EVENTOUT

43 K6 N4 66 N11 76 87 R12 PE13 I/O FT -

TIM1_CH3, SPI4_MISO,

SAI2_FS_B, FMC_D10,

LCD_DE, EVENTOUT

44 G7 M4 67 P11 77 88 P11 PE14 I/O FT -

TIM1_CH4, SPI4_MOSI,

SAI2_MCK_B, FMC_D11,

LCD_CLK, EVENTOUT

45 H7 L3 68 R11 78 89 R11 PE15 I/O FT -

TIM1_BKIN, FMC_D12,

LCD_R7, EVENTOUT

46 J7 M3 69 R12 79 90 P12 PB10 I/O FT -

TIM2_CH3, I2C2_SCL,

SPI2_SCK/I2S2_CK,

USART3_TX,

OTG_HS_ULPI_D3,

ETH_MII_RX_ER,

LCD_G4, EVENTOUT

47 K7 N3 70 R13 80 91 R13 PB11 I/O FT -

TIM2_CH4, I2C2_SDA,

USART3_RX,

OTG_HS_ULPI_D4,

ETH_MII_TX_EN/ETH_R

MII_TX_EN, LCD_G5,

EVENTOUT

48 F8 N2 71 M10 81 92 L11 VCAP_1 S - - - -

49 - H2 - - - 93 K9 VSS S - - - -

50 - J6 72 N10 82 94 L10 VDD S - - - -

- - - - - - 95 M14 PJ5 I/O FT - LCD_R6, EVENTOUT -

-- --M118396P13PH6I/OFT-

I2C2_SMBA, SPI5_SCK,

TIM12_CH1,

ETH_MII_RXD2,

FMC_SDNE1, DCMI_D8,

EVENTOUT

Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)

Pin Number

name

(function

after

reset)

(1)

Pin type

I/O structure

Notes

Alternate functions

Additional

functions

LQFP100

TFBGA100

WLCSP143

LQFP144

UFBGA176

LQFP176

LQFP208

TFBGA216

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