Datasheet
DocID027590 Rev 4 59/227
STM32F745xx STM32F746xx Pinouts and pin description
88
31 K3 L8 43 R3 53 56 R3 PA7 I/O FT
(4)
TIM1_CH1N, TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI/I2S1_SD,
TIM14_CH1,
ETH_MII_RX_DV/ETH_R
MII_CRS_DV,
FMC_SDNWE,
EVENTOUT
ADC12_IN7
32 G4 M8 44 N5 54 57 N5 PC4 I/O FT
(4)
I2S1_MCK,
SPDIFRX_IN2,
ETH_MII_RXD0/ETH_RM
II_RXD0, FMC_SDNE0,
EVENTOUT
ADC12_IN14
33 H4 N9 45 P5 55 58 P5 PC5 I/O FT
(4)
SPDIFRX_IN3,
ETH_MII_RXD1/ETH_RM
II_RXD1, FMC_SDCKE0,
EVENTOUT
ADC12_IN15
- - J7 - - - 59 L7 VDD S - - - -
- - - - - - 60 L6 VSS S - - - -
34 J4 N8 46 R5 56 61 R5 PB0 I/O FT
(4)
TIM1_CH2N, TIM3_CH3,
TIM8_CH2N,
UART4_CTS, LCD_R3,
OTG_HS_ULPI_D1,
ETH_MII_RXD2,
EVENTOUT
ADC12_IN8
35 K4 K7 47 R4 57 62 R4 PB1 I/O FT
(4)
TIM1_CH3N, TIM3_CH4,
TIM8_CH3N, LCD_R6,
OTG_HS_ULPI_D2,
ETH_MII_RXD3,
EVENTOUT
ADC12_IN9
36 G5 L7 48 M6 58 63 M5 PB2 I/O FT -
SAI1_SD_A,
SPI3_MOSI/I2S3_SD,
QUADSPI_CLK,
EVENTOUT
-
- - - - - - 64 G4 PI15 I/O FT - LCD_R0, EVENTOUT -
- - - - - - 65 R6 PJ0 I/O FT - LCD_R1, EVENTOUT -
- - - - - - 66 R7 PJ1 I/O FT - LCD_R2, EVENTOUT -
Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number
Pin
name
(function
after
reset)
(1)
Pin type
I/O structure
Notes
Alternate functions
Additional
functions
LQFP100
TFBGA100
WLCSP143
LQFP144
UFBGA176
LQFP176
LQFP208
TFBGA216
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