Datasheet
DocID027590 Rev 4 57/227
STM32F745xx STM32F746xx Pinouts and pin description
88
18 F3 J9 29 M5 35 38 L4 PC3 I/O FT
(4)
SPI2_MOSI/I2S2_SD,
OTG_HS_ULPI_NXT,
ETH_MII_TX_CLK,
FMC_SDCKE0,
EVENTOUT
ADC123_IN1
3
- - G7 30 G3 36 39 J5 VDD S - - - -
- - - - - - - J6 VSS S - - - -
19 G1 K10 31 M1 37 40 M1 VSSA S - - - -
- - - - N1 - - N1 VREF- S - - - -
20 - L11 32 P1 38 41 P1 VREF+ S - - - -
21 H1 L10 33 R1 39 42 R1 VDDA S - - - -
22 G2 K9 34 N3 40 43 N3
PA0-
WKUP(P
A0)
I/O FT
(5)
TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
USART2_CTS,
UART4_TX, SAI2_SD_B,
ETH_MII_CRS,
EVENTOUT
ADC123_IN0,
WKUP1
(4)
23 H2 K8 35 N2 41 44 N2 PA1 I/O FT
(4)
TIM2_CH2, TIM5_CH2,
USART2_RTS,
UART4_RX,
QUADSPI_BK1_IO3,
SAI2_MCK_B,
ETH_MII_RX_CLK/ETH_
RMII_REF_CLK,
LCD_R2, EVENTOUT
ADC123_IN1
24 J2 L9 36 P2 42 45 P2 PA2 I/O FT
(4)
TIM2_CH3, TIM5_CH3,
TIM9_CH1, USART2_TX,
SAI2_SCK_B,
ETH_MDIO, LCD_R1,
EVENTOUT
ADC123_IN2,
WKUP2
- - - - F4 43 46 K4 PH2 I/O FT
LPTIM1_IN2,
QUADSPI_BK2_IO0,
SAI2_SCK_B,
ETH_MII_CRS,
FMC_SDCKE0, LCD_R0,
EVENTOUT
-
Table 10. STM32F745xx and STM32F746xx pin and ball definition (continued)
Pin Number
Pin
name
(function
after
reset)
(1)
Pin type
I/O structure
Notes
Alternate functions
Additional
functions
LQFP100
TFBGA100
WLCSP143
LQFP144
UFBGA176
LQFP176
LQFP208
TFBGA216
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