Datasheet

DocID027590 Rev 4 181/227
STM32F745xx STM32F746xx Electrical characteristics
195
Figure 64. Synchronous non-multiplexed NOR/PSRAM read timings
Table 98. Synchronous non-multiplexed NOR/PSRAM read timings
(1)
Symbol Parameter Min Max Unit
t
w(CLK)
FMC_CLK period 2T
HCLK
−1 -
ns
t
(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x=0..2) - 2.5
t
d(CLKH-NExH)
FMC_CLK high to FMC_NEx high (x= 0…2) T
HCLK
+0.5 -
t
d(CLKL-NADVL)
FMC_CLK low to FMC_NADV low - 0
t
d(CLKL-NADVH)
FMC_CLK low to FMC_NADV high 0 -
t
d(CLKL-AV)
FMC_CLK low to FMC_Ax valid (x=16…25) - 2.5
t
d(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid (x=16…25) T
HCLK
-
t
d(CLKL-NOEL)
FMC_CLK low to FMC_NOE low - 2
t
d(CLKH-NOEH)
FMC_CLK high to FMC_NOE high T
HCLK
+0.5 -
t
su(DV-CLKH)
FMC_D[15:0] valid data before FMC_CLK high 1.5 -
t
h(CLKH-DV)
FMC_D[15:0] valid data after FMC_CLK high 1 -
t
(NWAIT-CLKH)
FMC_NWAIT valid before FMC_CLK high 2 -
t
h(CLKH-NWAIT)
FMC_NWAIT valid after FMC_CLK high 3.5 -
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