Datasheet

DocID027590 Rev 4 17/227
STM32F745xx STM32F746xx Functional overview
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2 Functional overview
2.1 ARM
®
Cortex
®
-M7 with FPU
The ARM
®
Cortex
®
-M7 with FPU processor is the latest generation of ARM processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and a low-power consumption, while
delivering an outstanding computational performance and low interrupt latency.
The Cortex
®
-M7 processor is a highly efficient high-performance featuring:
– Six-stage dual-issue pipeline
– Dynamic branch prediction
– Harvard caches (4 Kbytes of I-cache and 4 Kbytes of D-cache)
– 64-bit AXI4 interface
– 64-bit ITCM interface
– 2x32-bit DTCM interfaces
The processor supports the following memory interfaces:
• Tightly Coupled Memory (TCM) interface.
• Harvard instruction and data caches and AXI master (AXIM) interface.
• Dedicated low-latency AHB-Lite peripheral (AHBP) interface.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
Its single precision FPU (floating point unit) speeds up the software development by using
metalanguage development tools, while avoiding saturation.
Figure 2 shows the general block diagram of the STM32F745xx and STM32F746xx
devices.
Note: Cortex
®
-M7 with FPU core is binary compatible with the Cortex
®
-M4 core.
2.2 Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4
gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
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